Watchdog Toggle (Mode 10) - Freescale Semiconductor DSP56374 User Manual

each subsequent timer clock. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared). If the counter overflows, a pulse
is output on the TIO signal with a pulse width equal to the timer clock period. If the INV bit is set, the pulse polarity is high (logical 1). If INV
is cleared, the pulse polarity is low (logical 0). The counter reloads when the TLR is written with a new value while the TCSR[TE] bit is set.
In Mode 9, internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after the hardware RESET signal is
asserted. This convention ensures that a valid RESET signal is generated when the TIO signal resets the DSP56374.
Mode 9 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
float
TIO pin (INV = 0)
float
TIO pin (INV = 1)
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
9.3.4.2

Watchdog Toggle (Mode 10)

Bit Settings
TC3 TC2 TC1
1 0 1
In Mode 10, the timer toggles an external signal after a preset period. The TIO signal is set to the value of the INV bit.When the counter equals
the value in the TCPR, TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is also set. If the TCSR[TRM] bit is
set, the counter loads with the TLR value on the next timer clock and the count resumes. Therefore, TRM = 1 is not useful for watchdog
functions. If the TCSR[TRM] bit is cleared, the counter continues to increment on each subsequent timer clock. When a counter overflow
occurs, the polarity of the TIO output signal is inverted. The counter is reloaded whenever the TLR is written with a new value while the
TCSR[TE] bit is set. This process repeats until the timer is disabled. In Mode 10, internal logic preserves the TIO value and direction for an
additional 2.5 internal clock cycles after the hardware RESET signal is asserted. This convention ensures that a valid reset signal is generated
when the TIO signal resets the DSP56374.
Freescale Semiconductor
(Software does not reset watchdog timer; watchdog times out)
first event
N
0
N
N + 1
M
low
high
Figure 9-18. Watchdog Pulse Mode
Mode Characteristics
TC0 Mode
0 10
DSP56374 Users Guide, Rev. 1.2
TRM = 1 is not useful for watchdog function
M M + 1
Name Function
Toggle Watchdog
Operating Modes
0
1
pulse width
= timer
clock period
TIO Clock
Output Internal
9-17