Freescale Semiconductor DSP56374 User Manual page 162

Triple Timer Module Programming Model
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (continued)
Bit Number Bit Name
12 DI
11 DIR
10
9 TRM
8 INV
9-22
Reset Value
0 Data Input
Reflects the value of the TIO signal. If the INV bit is set, the value of the
TIO signal is inverted before it is written to the DI bit. If the INV bit is
cleared, the value of the TIO signal is written directly to the DI bit.
0 Direction
Determines the behavior of the TIO signal when it functions as a GPIO
signal. When DIR is set, the TIO signal is an output; when DIR is cleared,
the TIO signal is an input. The TIO signal functions as a GPIO signal only
when the TC[3–0] bits are cleared. If any of the TC[3–0] bits are set, then
the GPIO function is disabled, and the DIR bit has no effect.
0 Reserved. Write to zero for future compatibility.
0 Timer Reload Mode
Controls the counter preload operation. In timer (0–3) and watchdog (9–10)
modes, the counter is preloaded with the TLR value after the TCSR[TE] bit
is set and the first internal or external clock signal is received. If the TRM
bit is set, the counter is reloaded each time after it reaches the value
contained by the TCR. In PWM mode (7), the counter is reloaded each time
counter overflow occurs. In measurement (4–5) modes, if the TRM and the
TCSR[TE] bits are set, the counter is preloaded with the TLR value on each
appropriate edge of the input signal. If the TRM bit is cleared, the counter
operates as a free running counter and is incremented on each incoming
event.
0 Inverter
Affects the polarity definition of the incoming signal on the TIO signal when
TIO is programmed as input. It also affects the polarity of the output pulse
generated on the TIO signal when TIO is programmed as output. See
9-4. The INV bit does not affect the polarity of the prescaler source when
the TIO is input to the prescaler.
NOTE: The INV bit affects both the timer and GPIO modes of operation. To
ensure correct operation, change this bit only when one or both of the
following conditions is true: the timer is disabled (the TCSR[TE] bit is
cleared). The timer is in GPIO mode.
DSP56374 Users Guide, Rev. 1.2
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