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When programmed as input flags, the SCKR, FSR and HCKR logic values, respectively, are latched at the same time as the first bit of the
receive data word is sampled. Because the input was latched, the signal on the input flag pin (SCKR, FSR or HCKR) can change without
affecting the input flag until the first bit of the next receive data word. When the received data words are transferred to the receive data
registers, the input flag latched values are then transferred to the IF0, IF1 and IF2 bits in the SAISR register, where they may be read by
software.
When programmed as output flags, the SCKR, FSR and HCKR logic values are driven by the contents of the OF0, OF1 and OF2 bits in the
SAICR register respectively, and they are driven when the transmit data registers are transferred to the transmit shift registers. The value on
SCKR, FSR and HCKR is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data
word is transmitted. Software may change the OF0-OF2 values thus controlling the SCKR, FSR and HCKR pin values for each transmitted
word. The normal sequence for setting output flags when transmitting data is as follows: wait for TDE (transmitter empty) to be set; first write
the flags, and then write the transmit data to the transmit registers. OF0, OF1 and OF2 are double buffered so that the flag states appear on
the pins when the transmit data is transferred to the transmit shift register, i.e., the flags are synchronous with the data.
8.5
GPIO - Pins and Registers
The GPIO functionality of each ESAI port is controlled by three respective registers:
ESAI
Port C control register (PCRC)
Port C direction register (PRRC)
Port C data register (PDRC)
8.5.1
Port C (ESAI) GPIO - Pins and Registers
The GPIO functionality of the ESAI port is controlled by three registers: Port C control register (PCRC), Port C direction register (PRRC)
and Port C data register (PDRC).
8.5.1.1
Port C Control Register (PCRC)
The read/write 24-bit Port C Control Register (PCRC) in conjunction with the Port C Direction Register (PRRC) controls the functionality of
the ESAI GPIO pins. Each of the PC(11:0) bits controls the functionality of the corresponding port pin. See
configurations. Hardware and software reset clear all PCRC bits.
8.5.1.2
Port C Direction Register (PRRC)
The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionality of
the ESAI GPIO pins.
Table 8-12
Freescale Semiconductor
ESAI_1
Port E control register (PCRE)
Port E direction register (PRRE)
Port E data register (PDRE)
describes the port-pin configurations. Hardware and software reset clear all PRRC bits.
Table 8-12. PCRC and PRRC Bits Functionality
PDC[i]
PC[i]
0
0
0
1
1
0
1
1
DSP56374 Users Guide, Rev. 1.2
Port Pin[i] Function
Disconnected
GPIO input
GPIO output
ESAI
GPIO - Pins and Registers
Table 8-12
for the port-pin
8-35
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