Pll Out = Vco Out/2 [Od1 = 0, Od0 = 1] - Freescale Semiconductor DSP56374 User Manual

EXTAL
Predivider
1 to 31
PD[4–0]
Figure 5-6 displays how setting OD1 = 1 and OD0 = 0 divides the VCO output to generate a PLL Output that is VCO Out/2.
EXTAL
Predivider
1 to 31
PD[4–0]
Figure 5-7 displays how setting OD1 = 1 and OD0 = 1 divides the VCO output to generate a PLL Output that is VCO Out/4.
Freescale Semiconductor
Fref
Phase
Charge Pump
Detector and
Loop Filter
Frequency
Divider
MF[7–0] 1 to 255
Figure 5-5. PLL Out = VCO Out/2 [OD1 = 0, OD0 = 1]
Fref
Phase
Charge Pump
Detector
and
Loop Filter
Frequency
Divider
MF[7–0] 1 to 255
Figure 5-6. PLL Out = VCO Out/2 [OD1 = 1, OD0 = 0]
DSP56374 Users Guide, Rev. 1.2
OD1
VCO Out
0
VCO
1
Divide
by 2
FM
Divide
by 2
0
PLL Out
1
OD0
NOTE:
5 MHz < Fref < 20 MHz
300 MHz < VCO Out< 600 MHz
OD1
VCO Out
0
VCO
1
Divide
by 2
FM
Divide
by 2
0
PLL Out
1
OD0
NOTE:
5 MHz < Fref < 20 MHz
300 MHz < VCO Out< 600 MHz
PLL Operation
Clock
Generator
0
1
PEN
Clock
Generator
0
1
PEN
5-5