Freescale Semiconductor DSP56374 User Manual page 5

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6.2.1 Port C and E Signals and Registers .....................................................................................................................6-1
6.2.2 Port G Signals and Registers ...............................................................................................................................6-1
6.2.2.1 Port G Control Register (PCRG) ..................................................................................................................6-1
6.2.2.2 Port G Direction Register (PRRG) ...............................................................................................................6-1
6.2.2.3 Port G Data register (PDRG) ........................................................................................................................6-2
6.2.2.4 ESAI/EXTAL clocking control ....................................................................................................................6-2
6.2.3 Port H Signals and Registers ...............................................................................................................................6-3
6.2.3.1 Port H Control Register (PCRH) ..................................................................................................................6-3
6.2.3.2 Port H Direction Register (PRRH) ...............................................................................................................6-3
6.2.3.3 Port H Data register (PDRH) ........................................................................................................................6-4
6.2.4 Timer/Event Counter Signals ..............................................................................................................................6-4
7.1 Introduction ...............................................................................................................................................................7-1
7.2 Serial Host Interface Internal Architecture ...............................................................................................................7-1
7.3 SHI Clock Generator .................................................................................................................................................7-2
7.4 Serial Host Interface Programming Model ...............................................................................................................7-2
7.4.1 SHI Input/Output Shift Register (IOSR)-Host Side .........................................................................................7-4
7.4.2 SHI Host Transmit Data Register (HTX)-DSP Side ........................................................................................7-4
7.4.3 SHI Host Receive Data FIFO (HRX)-DSP Side ..............................................................................................7-5
7.4.4 SHI Slave Address Register (HSAR)-DSP Side ..............................................................................................7-5
7.4.4.1 HSAR Reserved Bits-Bits 19, 17- 0 ..........................................................................................................7-5
7.4.4.2 HSAR I
7.4.5 SHI Clock Control Register (HCKR)-DSP Side ..............................................................................................7-5
7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)-Bits 1-0 ............................................................................7-5
7.4.5.2 HCKR Prescaler Rate Select (HRS)-Bit 2 .................................................................................................7-6
7.4.5.3 HCKR Divider Modulus Select (HDM[7:0])-Bits 10-3 ............................................................................7-7
7.4.5.4 HCKR Filter Mode (HFM[1:0]) - Bits 13-12 ............................................................................................7-7
7.4.5.5 HCKR Reserved Bits-Bits 23-14, 11 ........................................................................................................7-7
7.4.6 SHI Control/Status Register (HCSR)-DSP Side ..............................................................................................7-7
7.4.6.1 HCSR Host Enable (HEN)-Bit 0 ...............................................................................................................7-7
7.4.6.1.1
7.4.6.2 HCSR I
7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])-Bits 3-2 ............................................................................7-8
7.4.6.4 HCSR I
7.4.6.5 HCSR FIFO-Enable Control (HFIFO)-Bit 5 .............................................................................................7-8
7.4.6.6 HCSR Master Mode (HMST)-Bit 6 ...........................................................................................................7-8
7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])-Bits 8-7 .................................................................................7-9
7.4.6.8 HCSR Idle (HIDLE)-Bit 9 .........................................................................................................................7-9
7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)-Bit 10 .....................................................................................7-9
7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)-Bit 11 ......................................................................................7-9
7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])-Bits 13-12 .......................................................................7-10
7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)-Bit 14 ............................................................................7-10
7.4.6.13 HCSR Host Transmit Data Empty (HTDE)-Bit 15 .................................................................................7-10
7.4.6.14 HCSR Reserved Bits-Bits 23, 18 and 16 .................................................................................................7-10
7.4.6.15 Host Receive FIFO Not Empty (HRNE)-Bit 17 ......................................................................................7-10
7.4.6.16 Host Receive FIFO Full (HRFF)-Bit 19 ..................................................................................................7-10
7.4.6.17 Host Receive Overrun Error (HROE)-Bit 20 ...........................................................................................7-11
Freescale Semiconductor
Chapter 7
Serial Host Interface
2
C Slave Address (HA[6:3], HA1)-Bits 23-20,18 .......................................................................7-5
SHI Individual Reset ..............................................................................................................................7-8
2
C/SPI Selection (HI2C)-Bit 1 ......................................................................................................7-8
2
C Clock Freeze (HCKFR)-Bit 4 ..................................................................................................7-8
DSP56374 Users Guide, Rev. 1.2
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