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PLL Initialization Procedure
Table 5-3. PLL Control (PCTL) Register Bit Definitions (continued)
Bit Number
Bit Name
7–0
MF[7–0]
a
The reset value of the PEN bit is based on the value of the PLL PINIT input
5.8
PLL Initialization Procedure
The DSP56374 PLL is programmed via the PCTL register. Unlike the DSP56371, the DSP56374 does not require a two step initialization
process. However, the DSP56374 PLL is backwards compatible with the DSP56371 and will support the two step initialization process. The
following programming example illustrates the initialization process.
PLL Programming Example:
Input Frequency (EXTAL) - 24.576 MHz
Target Operating Frequency - 150 MHz
Program the PLL control register (PCTL) - $23E012.
-
This enables the TIO2/PLOCK pin as a PLOCK pin
-
This multiplies up the input frequency to a VCO frequency of 589.824 MHz
-
The PLL output is VCO / 4 via the output divider to 147.456 MHz
-
The Fosc frequency is VCO / 4 via the output divider and low power divider to 147.456 MHz
Note that the default PCTL value is $04601D.
Use
Table 5-5
to determine the appropriate PCTL value for generating the maximum operating frequency (Fosc). Locate the maximum Fref
value in the table that is larger than the target Fref. Use the corresponding final PCTL value to generate the maximum operating frequency
given the target Fref.
5-10
Reset
Value
$1D
Multiplication Factor
Defines the Multiplication Factor (MF) that is applied to the PLL input frequency.
The MF can be any integer from 1 to 255. The VCO oscillates at a frequency
defined by the following formula where PDF is the Predivider Division Factor and
FM is the Feedback Multiplier:
The MF must be chosen to ensure that the resulting VCO output frequency is in
the range specified in the device-specific technical data sheet (300 MHz - 600
MHz). Any time a new value is written into the MF[7–0] bits, the PLL loses the
lock condition. The Multiplication Factor bits MF[7–0] are set to $1D (29) during
hardware reset.
Table 5-5. PCTL Value Guide
150 MHz
Maximum Fref
(MHz)
1
5.00
2
5.15
3
5.35
4
5.55
5
5.75
6
6.00
7
6.25
DSP56374 Users Guide, Rev. 1.2
Description
Fextal MF FM
(
×
×
)
---------------------------------------------- -
PDF
Final PCTL
$2xE01E
$2xE01D
$2xE01C
$2xE01B
$2xE01A
$2xE019
$2xE018
Freescale Semiconductor
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