Appendix C Programmer's Reference; Introduction; Peripheral Addresses; Interrupt Addresses - Freescale Semiconductor DSP56374 User Manual

Appendix C
Programmer's Reference
C.1

Introduction

This section has been compiled as a reference for programmers. It contains a table showing the addresses of all the DSPs memory-mapped
peripherals, an interrupt address table, an interrupt exception priority table, and programming sheets for the major programmable registers on
the DSP.
C.1.1

Peripheral Addresses

Figure C-1. lists the memory addresses of all on-chip peripherals.
C.1.2

Interrupt Addresses

Figure C-2. lists the interrupt starting addresses and sources.
C.1.3

Interrupt Priorities

Figure C-3. lists the priorities of specific interrupts within interrupt priority levels.
C.1.4

Programming Sheets

The remaining figures describe major programmable registers on the DSP56374.
C.1.5

Internal I/O Memory Map

Peripheral
IPR
PLL
ONCE
BIU
DMA
DMA0
DMA1
Freescale Semiconductor
Table C-1. Internal I/O Memory Map (X Memory)
Address
X:$FFFFFF INTERRUPT PRIORITY REGISTER CORE (IPR-C)
X:$FFFFFE INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P)
X:$FFFFFD PLL CONTROL REGISTER (PCTL)
X:$FFFFFC ONCE GDB REGISTER (OGDB)
X:$FFFFFB BCR
X:$FFFFFA RESERVED
X:$FFFFF9 RESERVED
X:$FFFFF8 RESERVED
X:$FFFFF7 RESERVED
X:$FFFFF6 RESERVED
X:$FFFFF5 ID Register (IDR)
X:$FFFFF4 DMA STATUS REGISTER (DSTR)
X:$FFFFF3 DMA OFFSET REGISTER 0 (DOR0)
X:$FFFFF2 DMA OFFSET REGISTER 1 (DOR1)
X:$FFFFF1 DMA OFFSET REGISTER 2 (DOR2)
X:$FFFFF0 DMA OFFSET REGISTER 3 (DOR3)
X:$FFFFEF DMA SOURCE ADDRESS REGISTER (DSR0)
X:$FFFFEE DMA DESTINATION ADDRESS REGISTER (DDR0)
X:$FFFFED DMA COUNTER (DCO0)
X:$FFFFEC DMA CONTROL REGISTER (DCR0)
X:$FFFFEB DMA SOURCE ADDRESS REGISTER (DSR1)
X:$FFFFEA DMA DESTINATION ADDRESS REGISTER (DDR1)
X:$FFFFE9 DMA COUNTER (DCO1)
X:$FFFFE8 DMA CONTROL REGISTER (DCR1)
DSP56374 Users Guide, Rev. 1.2
Register Name
Introduction
C-1