Timer Toggle (Mode 2) - Freescale Semiconductor DSP56374 User Manual

Mode 1 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
TOF (Overflow Interrupt if TCIE = 1)
9.3.1.3

Timer Toggle (Mode 2)

Bit Settings
TC3 TC2 TC1
0 0 1
In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is enabled, the TIO signal is loaded with the value of
the TCSR[INV] bit. When the counter value matches the value in the TCPR, the polarity of the TIO output signal is inverted. TCSR[TCF] is
set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is loaded with the value of
the TLR when the next timer clock is received, and the count resumes. If the TRM bit is cleared, the counter continues to increment on each
timer clock. This process repeats until the timer is cleared (disabling the timer). The TCPR[TLR] value sets the delay between starting the
timer and toggling the TIO signal. To generate output signals with a delay of X clock cycles between toggles, set the TLR value to X/2, and
set the TCSR[TRM] bit. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared).
Freescale Semiconductor
first event
N
0 N
N + 1
M
Figure 9-6. Pulse Mode (TRM = 0)
Mode Characteristics
TC0 Mode Name
0 2 Toggle
DSP56374 Users Guide, Rev. 1.2
M + 1 0
M
pulse width =
timer clock
period
Function
Timer
Operating Modes
1
TIO Clock
Output Internal
9-7