Freescale Semiconductor DSP56374 User Manual page 72

PLL Programming Model
Bit Number Bit Name
21 PLKM
20–16 PD[4–0]
15–14 OD[1–0]
5-8
Table 5-3. PLL Control (PCTL) Register Bit Definitions
Reset
Value
$0 PLL LOCK MUX
The PLOCK Mux (PLKM) bit is a read/write bit that controls the operation of the
PLOCK/TIO2 pin. When PLKM is set, the PLOCK/TIO2 pin operates as the PLL
lock indicator (PLOCK). When the PLKM bit is cleared, the PLOCK/TIO2 pin
operates as the TIO2 pin.
NOTE: The PLKM bit is set during hardware reset.
$4 Predivider Factor
Defines the PDF value that is applied to the input frequency. PDF can be any
integer from 1 to 31. The VCO is a function of PDF and oscillates at a frequency
defined by the following formula:
PDF must be chosen to ensure that Fref lies in a range specified in the
device-specific technical data sheet (5 MHz - 20 MHz) and the resulting VCO
output frequency lies in the range specified in the device-specific technical data
sheet (300 MHz - 600 MHz). Any time a new value is written into the PD[4–0] bits,
the PLL loses the lock condition. The PDF bits (PD[4–0]) are set to $4 during
hardware reset. The PDF value should never be set to $0.
01 Output Divider Factor and Feedback Multiplier
Defines the OD and FM values that are applied to the output VCO frequency. The
VCO oscillates at a frequency defined by the following formula:
FM = 2(1 + OD1). OD1 must be chosen to ensure that the resulting VCO output
frequency lies in the range specified in the device-specific technical data sheet
(300 MHz - 600 MHz). Any time OD1 is changed, the PLL loses the lock
condition.
OD1 is initially cleared (0) following reset. OD0 is initially set (1) following reset.
Changes to OD0 do not cause the PLL to lose the lock condition. OD0 and OD1
bits together define the output divide factor (OD). The output divide factor divides
the VCO output frequency by a factor of 2 or 4 according to
Note that OD0 and OD1 should not simultaneously be cleared. The resulting
Fosc frequency will exceed the maximum operating frequency when in this case.
The PLL Output is defined by the following formula when OD = 1:
DSP56374 Users Guide, Rev. 1.2
Description
Fextal MF FM
( × ×
------------------------------------------------ -
PDF
Fextal MF FM
( × ×
---------------------------------------------- -
PDF
Table 5-4. Output Divide Factor (OD)
OD0 OD1
0 0
0 1
1 0
1 1
VCO Out
------------------------- -
OD
)
)
Table 5-4.
OD
Reserved
Div by 2
Div by 2
Div by 4
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