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11
TS27
23
The ESAI TSMA and TSMB registers are located at x:$FFFFB9 and x:$FFFFBA respectively. The ESAI_1 TSMA and TSMB registers are
located at y:$FFFF99 and y:$FFFF9A respectively.
When bit number N in TSM is cleared, all the transmit data pins of the enabled transmitters are tri-stated during transmit time slot number N.
The data is still transferred from the transmit data registers to the transmit shift registers but neither the TDE nor the TUE flags are set. This
means that during a disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled slots. Data that is written
to the transmit data registers when servicing this request is transmitted in the next enabled transmit time slot.
When bit number N in TSM register is set, the transmit sequence is as usual: data is transferred from the TX registers to the shift registers and
transmitted during slot number N, and the TDE flag is set.
Using the slot mask in TSM does not conflict with using TSR. Even if a slot is enabled in TSM, the user may chose to write to TSR instead
of writing to the transmit data registers TXx. This causes all the transmit data pins of the enabled transmitters to be tri-stated during the next
slot.
Data written to the TSM affects the next frame transmission. The frame being transmitted is not affected by this data and would comply to
the last TSM setting. Data read from TSM returns the last written data.
After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data
transmission.
When operating in normal mode, bit 0 of the mask register must be set, otherwise no output is
generated.
8.3.13
Receive Slot Mask Registers (RSMA, RSMB)
The Receive Slot Mask Registers (RSMA and RSMB) are two read/write registers used by the receiver in network mode to determine for each
slot whether to receive a data word and generate a receiver full condition (RDF=1), or to ignore the received data. RSMA and RSMB should
be considered as each containing half of a 32-bit register RSM. See
enable/disable control bit for receiving data in slot number N.
11
RS11
23
Freescale Semiconductor
10
9
8
7
TS26
TS25
TS24
TS23
22
21
20
19
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-16. TSMB Register
NOTE
10
9
8
7
RS10
RS9
RS8
RS7
22
21
20
19
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-17. RSMA Register
DSP56374 Users Guide, Rev. 1.2
6
5
4
TS22
TS21
TS20
TS19
18
17
16
TS31
Table 8-17
and
Table
8-18. Bit number N in RSM (RS**) is an
6
5
4
RS6
RS5
RS4
RS3
18
17
16
RS15
ESAI Programming Model
3
2
1
0
TS18
TS17
TS16
15
14
13
12
TS30
TS29
TS28
3
2
1
0
RS2
RS1
RS0
15
14
13
12
RS14
RS13
RS12
8-31
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