Tcr Transmit Frame Sync Length (Tfsl) - Bit 15 - Freescale Semiconductor DSP56374 User Manual

ESAI Programming Model
TSWS4 TSWS3
0 0
0 0
0 0
0 1
0 0
0 0
0 1
0 1
0 0
0 0
1 0
0 1
0 1
0 0
1 1
1 1
1 0
1 0
0 1
1 1
0 1
0 1
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
8.3.2.11

TCR Transmit Frame Sync Length (TFSL) - Bit 15

The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL
is set, a 1-bit clock period frame sync is selected. See
8-14
Table 8-5. ESAI Transmit Slot and Word Length Selection
TSWS2 TSWS1
0 0
1 0
0 0
0 0
1 0
0 1
1 0
0 0
1 1
0 1
0 0
1 0
0 1
1 1
1 1
0 0
1 0
0 1
1 1
1 1
0 1
1 1
0 0
0 1
1 0
1 1
1 1
0 0
0 1
0 1
1 0
1 0
Figure 8-7
DSP56374 Users Guide, Rev. 1.2
TSWS0 SLOT LENGTH
0 8
0 12
1
0 16
1
0
0 20
1
0
1
0 24
1
0
1
0
0 32
1
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
for examples of frame length selection.
WORD LENGTH
8
8
12
8
12
16
8
12
16
20
8
12
16
20
24
8
12
16
20
24
Reserved
Freescale Semiconductor