Freescale Semiconductor DSP56374 User Manual page 189

M_D4L EQU $300000
M_D4L0 EQU 20
M_D4L1 EQU 21
M_D5L EQU $C00000
M_D5L0 EQU 22
M_D5L1 EQU 23
; Interrupt Priority Register Peripheral (IPRP)
M_ESL EQU $3
M_ESL0 EQU 0
M_ESL1 EQU 1
M_SHL EQU $C
M_SHL0 EQU 2
M_SHL1 EQU 3
M_DAL EQU $C0
M_DAL0 EQU 6
M_DAL1 EQU 7
M_TAL EQU $300
M_TAL0 EQU 8
M_TAL1 EQU 9
M_ES1L EQU $C00 ; ESAI_1 Interrupt Priority Level Mask
M_ESL10 EQU 10
M_ESL11 EQU 11
M_EFC EQU $30000 ; EFCOP Interrupt Priority Level Mask
M_EFC0 EQU 16
M_EFC1 EQU 17
;------------------------------------------------------------------------
;
; EQUATES for Direct Memory Access (DMA)
;
;------------------------------------------------------------------------
; Register Addresses Of DMA
M_DSTR EQU $FFFFF4
M_DOR0 EQU $FFFFF3
M_DOR1 EQU $FFFFF2
M_DOR2 EQU $FFFFF1
M_DOR3 EQU $FFFFF0
; Register Addresses Of DMA0
M_DSR0 EQU $FFFFEF
M_DDR0 EQU $FFFFEE
M_DCO0 EQU $FFFFED
M_DCR0 EQU $FFFFEC
; Register Addresses Of DMA1
M_DSR1 EQU $FFFFEB
M_DDR1 EQU $FFFFEA
M_DCO1 EQU $FFFFE9
M_DCR1 EQU $FFFFE8
Freescale Semiconductor
; DMA4 Interrupt priority Level Mask
; DMA4 Interrupt Priority Level (low)
; DMA4 Interrupt Priority Level (high)
; DMA5 Interrupt priority Level Mask
; DMA5 Interrupt Priority Level (low)
; DMA5 Interrupt Priority Level (high)
; ESAI Interrupt Priority Level Mask
; ESAI Interrupt Priority Level (low)
; ESAI Interrupt Priority Level (high)
; SHI Interrupt Priority Level Mask
; SHI Interrupt Priority Level (low)
; SHI Interrupt Priority Level (high)
; DAX Interrupt Priority Level Mask
; DAX Interrupt Priority Level (low)
; DAX Interrupt Priority Level (high)
; Timer Interrupt Priority Level Mask
; Timer Interrupt Priority Level (low)
; Timer Interrupt Priority Level (high)
; ESAI_1 Interrupt Priority Level (low)
; ESAI_1 Interrupt Priority Level (high)
; EFCOP Interrupt Priority Level (low)
; EFCOP Interrupt Priority Level (high)
; X space: DMA Status Register
; X space: DMA Offset Register 0
; X space: DMA Offset Register 1
; X space: DMA Offset Register 2
; X space: DMA Offset Register 3
; X space: DMA0 Source Address Register
; X space: DMA0 Destination Address Register
; X space: DMA0 Counter
; X space: DMA0 Control Register
; X space: DMA1 Source Address Register
; X space: DMA1 Destination Address Register
; X space: DMA1 Counter
; X space: DMA1 Control Register
DSP56374 Users Guide, Rev. 1.2
B-5