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Motorola MVME162LX 300 Series Installation And Use Manual

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MVME162LX 200/300 Series
Embedded Controller
Installation and Use
V162LX2-3A/IH3

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  Summary of Contents for Motorola MVME162LX 300 Series

  • Page 1 MVME162LX 200/300 Series Embedded Controller Installation and Use V162LX2-3A/IH3...
  • Page 2 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 3 MVME162LX-3xx (200 and 300 series) models that are currently shipping as of the publication date of this manual. ® Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. All other products mentioned in this document are trademarks or registered trademarks of their respective holders. © Copyright Motorola, Inc. 1998...
  • Page 4 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 5 Low Voltage Directive (73/23/EEC). In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file at Motorola, Inc. - Computer Group, 27 Market Street, Maidenhead, United Kingdom, SL6 8AE. This board product was tested in a representative system to show compliance with the above mentioned requirements.
  • Page 7: Table Of Contents

    Contents CHAPTER 1 Board Level Hardware Description Introduction........................1-1 Overview......................1-1 Related Documentation..................1-2 Models Available ....................1-3 Document Requirements..................1-4 Available Software....................1-5 Required Equipment ...................1-5 Features.......................1-5 Specifications......................1-7 Cooling Requirements ..................1-8 Special Considerations for Elevated-Temperature Operation ......1-9 Manual Terminology..................1-10 Block Diagram ......................1-11 Functional Description.....................1-12 Switches and LEDs...................1-12 ABORT Switch..................1-12 RESET Switch ...................1-12 Front Panel Indicators................1-13...
  • Page 8 Local Resources ....................1-22 Programmable Tick Timers............... 1-22 Watchdog Timer..................1-22 Software-Programmable Hardware Interrupts .......... 1-23 Local Bus Timeout ..................1-23 Local Bus Arbiter ..................... 1-24 Connectors......................1-24 Memory Maps......................1-25 Local Bus Memory Map................... 1-25 Normal Address Range ................1-25 Detailed I/O Memory Maps ................
  • Page 9 CHAPTER 3 Debugger General Information Overview ........................3-1 Description of 162Bug ....................3-1 162Bug Implementation.....................3-2 Installation and Start-up .....................3-3 Autoboot ........................3-6 ROMboot ........................3-7 Network Boot ......................3-8 Restarting the System ....................3-9 Reset........................3-9 Abort .........................3-10 Break .........................3-10 SYSFAIL* Assertion/Negation ................3-10 MPU Clock Speed Calculation .................3-11 Memory Requirements.....................3-11 Terminal Input/Output Control ................3-12 Disk I/O Support ......................3-13...
  • Page 10 CHAPTER 4 Using The 162Bug Debugger Entering Debugger Command Lines ................. 4-1 Syntactic Variables ..................... 4-2 Expression as a Parameter................4-3 Address as a Parameter ................4-4 Address Formats..................4-4 Offset Registers................... 4-6 Port Numbers...................... 4-8 Entering and Debugging Programs................4-9 Calling System Utilities from User Programs ............
  • Page 11 IndustryPack I/O Interconnections ................I-4 Remote Reset/LED Interconnection ................I-5 VME Bus Interconnection ..................I-6 Connector P1 Interconnect Signals..............I-6 Connector P2 Interconnect Signals..............I-10 APPENDIX J Related Documentation Motorola Documentation ................... J-1 Non-Motorola Documentation................... J-2 Support Information ....................J-3...
  • Page 12 FIGURES Figure 1-1. MVME162LX Block Diagram ............. 1-11 Figure 2-1. MVME162LX Switch, Header, Connector, Fuse, and LED Locations.. 2-3 Figure 2-2. DB25-DTE-to-RJ45 Adapter..............2-16 Figure 2-3. DB25-DCE-to-RJ45 Adapter..............2-17 Figure 2-4. Typical RJ45 Serial Cable..............2-17 Figure D-1. Serial Interface Connections ..............D-2 Figure D-2.
  • Page 13 Table 4-3. Debugger Commands ................4-20 Table A-1. ENV Command Parameters ..............A-4 Table D-1. Connector J17 Interconnect Signals ............D-1 Table E-1. Ethernet Connector J9 Interconnect Signals ......... E-1 Table F-1. SCSI Connector J10 Interconnect Signals ..........F-1 Table G-1. Mezzanine Connector J15 Interconnect Signals ........G-1 Table G-2.
  • Page 15: Introduction

    1Board Level Hardware Description Introduction This chapter provides a board-level hardware description of the MVME162LX Embedded Controller. It contains a general overview of the product along with a list of hardware features and a detailed functional description. The controller’s front panel switches and indicators are included in the functional description.
  • Page 16: Related Documentation

    Board Level Hardware Description Input/Output (I/O) signals are routed through industry standard connectors on the controller’s front panel. This includes the I/O for the serial ports, which is provided by four RJ45 connectors. The VMEbus interface is provided by an ASIC called the VMEchip2. It contains two tick timers, a watchdog timer, programmable map decoders for the master and slave interfaces, a VMEbus to/from local bus DMA controller, a VMEbus to/from local bus non-DMA programmed access...
  • Page 17: Models Available

    Introduction Models Available As of the publication date of this manual, the MVME162LX Embedded Controller is available in a number of models shown in Table 1-1. Table 1-1. MVME162LX Embedded Controller Models Model Description -200 MC68LC040 25 MHz microprocessor, 1 MB DRAM, 128 KB SRAM,1 MB Flash memory, 2 IndustryPack sites -201 MC68LC040 25 MHz microprocessor, 1 MB DRAM,...
  • Page 18: Document Requirements

    Board Level Hardware Description Table 1-1. MVME162LX Embedded Controller Models (Continued) Model Description -243 MC68040 25 MHz microprocessor, 4 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 serial ports, SCSI & Ethernet -253 MC68LC040 25 MHz microprocessor, 16 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 serial ports, SCSI &...
  • Page 19: Available Software

    Available software for the controller includes the on-board debugger/monitor firmware, VMEexec driver packages for various IndustryPack modules, and numerous third-party applications for MC680x0-based systems. Contact your local Motorola sales office or distribution for more information. Required Equipment The following equipment is required to complete an MVME162LX system:...
  • Page 20 Board Level Hardware Description Feature Description Models Watchdog timer Provided in MCchip ASIC (VMEchip2) All models Serial I/O EIA-232-D DTE serial interface with four See Table 1-1 serial ports (Zilog Z85230 controller chips) SCSI I/O Optional Small Computer Systems Interface See Table 1-1 (SCSI) bus interface with 32-bit local bus burst Direct Memory Access (DMA) (NCR...
  • Page 21: Specifications

    Introduction Specifications Table 1-2 lists the specifications for an MVME162LX Embedded Controller without IndustryPacks. Table 1-2. MVME162LX Specifications Characteristics Specifications Power requirements +5Vdc (± 5%), 3.5 A typical, 4.5 A maximum (with EPROMs; without IPs) +12 Vdc (± 5%), 100 mA maximum -12 Vdc (±...
  • Page 22: Cooling Requirements

    (32° to 131° F). This is accomplished with forced air cooling at a velocity typically achievable by a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis. 25 watt load boards are inserted in two card slots (one on each side), adjacent to the board under test, to simulate a high power density system configuration.
  • Page 23: Special Considerations For Elevated-Temperature Operation

    Introduction Special Considerations for Elevated-Temperature Operation This section provides information pertinent to users whose applications for the MVME162LX Embedded Controller may subject it to high temperatures. The controller’s design uses commercial grade devices. Therefore, it can operate within an air temperature range of 0° C to 70° C. There are many factors that affect the ambient temperature felt by components on the controller: inlet air temperature;...
  • Page 24: Manual Terminology

    Board Level Hardware Description Manual Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: dollar specifies a hexadecimal character percent specifies a binary number & ampersand specifies a decimal number For example, "12"...
  • Page 25: Block Diagram

    Block Diagram Block Diagram Figure 1-1. MVME162LX Block Diagram http://www.mcg.mot.com/literature 1-11...
  • Page 26: Functional Description

    Board Level Hardware Description Functional Description This section contains a functional description of the MVME162LX Embedded Controller. Switches and LEDs The controller’s front panel has an switch and four ABORT RESET light-emitting diode (LED) indicators ( FAIL SCON FUSES ABORT Switch When enabled by software, the switch generates an interrupt at a ABORT...
  • Page 27: Front Panel Indicators

    Functional Description Similarly, the VMEchip2 provides an input signal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation.
  • Page 28: Mc68040 Or Mc68Lc040 Cpu

    Board Level Hardware Description MC68040 or MC68LC040 CPU The MC68040 or MC68LC040 processor is used on the MVME162LX. The MC68040 has on-chip instruction and data caches and a floating point processor. The major difference between the two processors is that the MC68040 has a floating point coprocessor.
  • Page 29: Memory Options

    Functional Description Memory Options The following memory options are used on the different versions of MVME162LX Embedded Controller boards. DRAM Options The controller offers various DRAM options (see Table 1-1): either 1 MB or 4 MB of parity-protected DRAM, or 4, 8, 16, or 32 MB ECC DRAM on a mezzanine board.
  • Page 30 Board Level Hardware Description The battery backup function for the onboard SRAM is provided by a Dallas DS1210S device that supports primary and secondary power sources. In the event of a main board power failure, the DS1210S checks power sources and switches to the source with the higher voltage. If the voltage of the backup source is less than two volts, the DS1210S blocks the second memory cycle;...
  • Page 31: Sram Batteries

    Functional Description SRAM Batteries Lithium batteries incorporate inflammable materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open Caution and ignite, possible resulting in injury and/or fire. When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents.
  • Page 32: Eprom And Flash Memory

    Board Level Hardware Description When a controller is stored, the battery should be disconnected to prolong battery life. This is especially important at high ambient temperatures. The controller is shipped with the batteries disconnected (with VMEbus +5V standby voltage selected as both primary and secondary power source). If you intend to use the battery as a power source, whether primary or secondary, it is necessary to reconfigure the jumpers on J13 before installing the module.
  • Page 33: Vmebus Interface And Vmechip2

    Functional Description VMEbus Interface and VMEchip2 The local bus to VMEbus interface, VMEbus to local bus interface, and the DMA controller functions of the local VMEbus are provided by the VMEchip2. The VMEchip2 can also provide the VMEbus system controller functions. Refer to the VMEchip2 in the MVME162LX Embedded Controller Programmer’s Reference Guide for additional programming information.
  • Page 34: Industrypack (Ip) Interfaces

    Board Level Hardware Description The Z85230 supplies an interrupt vector during interrupt acknowledge cycles. The vector is modified based upon the interrupt source within the Z85230. Interrupt request levels are programmed via the MCchip. The Z85230s are interfaced as DTE (data terminal equipment) with EIA- 232-D signal levels.
  • Page 35: Scsi Interface

    Functional Description Each board has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the Ethernet address are stored in the configuration area of the BBRAM. That is, 08003E2XXXXX is stored in the BBRAM. At an address of $FFFC1F2C, the upper four bytes (08003E2X) can be read.
  • Page 36: Local Resources

    Board Level Hardware Description The controller provides +5 Vdc to the SCSI bus TERMPWR signal through fuse F4, located near J7. The FUSES LED (part of DS2) on the MVME162LX front panel monitors the SCSI bus TERMPWR signal in addition to LAN power; with the controller connected to an SCSI bus, the FUSES LED lights when SCSI terminator power is present.
  • Page 37: Software-Programmable Hardware Interrupts

    Functional Description The watchdog timer logic is duplicated in the VMEchip2 and MCchip ASICs. Because the watchdog timer function in the VMEchip2 is a superset of that function in the MCchip (system reset function), the timer in the VMEchip2 is used in all cases except for the version of the MVME162LX which does not include the VMEbus interface ("No VMEbus Interface"...
  • Page 38: Local Bus Arbiter

    Board Level Hardware Description Local Bus Arbiter The local bus arbiter implements a fixed priority which is described in the following table. Table 1-3. Local Bus Arbitration Priority Device Priority Note Highest SCSI VMEbus Next Lowest MC68XX040 Lowest Connectors The MVME162LX Embedded Controller has two 96-position DIN connectors: P1 and P2.
  • Page 39: Memory Maps

    Memory Maps Memory Maps There are two points of view for memory maps: 1. The mapping of all resources as viewed by local bus masters (local bus memory map). 2. The mapping of onboard resources as viewed by external masters (VMEbus memory map).
  • Page 40: Table 1-4. Local Bus Memory Map

    Board Level Hardware Description Table 1-4. Local Bus Memory Map Address Range Devices Accessed Port Size Software Notes Width Cache Inhibit Programmable DRAM on Parity 1MB-4MB Mezzanine Programmable DRAM on ECC 16MB Mezzanine Programmable On-Board SRAM 128KB 2, 7 Programmable SRAM on Mezzanine 2, 7 Programmable...
  • Page 41 Memory Maps Notes 1. Devices mapped at $FFF80000-$FFF9FFFF also appear at $00000000- $001FFFFF when the ROM0 bit in the MCchip EPROM control register is high (ROM0=1). ROM0 is set to 1 after each reset. The ROM0 bit must be cleared before other resources (DRAM or SRAM) can be mapped in this range ($00000000 - $001FFFFF).
  • Page 42: Table 1-5. Local I/O Devices Memory Map

    Board Level Hardware Description The following table focuses on the ‘‘Local I/O Devices’’ portion of the local bus main memory map. Note The IPIC chip on the MVME162LX supports up to four IndustryPack (IP) interfaces, designated IP_a through IP_d. The MVME162LX itself accommodates two IPs: IP_a and IP_b.
  • Page 43 Memory Maps Table 1-5. Local I/O Devices Memory Map (Continued) Address Range Devices Accessed Port Size Notes Width $FFF58200 - $FFF5827F IPIC IP_c I/O 128 B $FFF58280 - $FFF582FF IPIC IP_c ID 128 B $FFF58300 - $FFF5837F IPIC IP_d I/O 128 B $FFF58380 - $FFF583FF IPIC IP_d ID Read...
  • Page 44 Board Level Hardware Description Table 1-5. Local I/O Devices Memory Map (Continued) Address Range Devices Accessed Port Size Notes Width $FFFCC000 - $FFFCFFFF MK48T08 & Enable D32-D8 16 KB 1, 7 Flash writes $FFFD0000 - $FFFEFFFF Reserved 128 KB Notes 1. For a complete description of the register bits, refer to the data sheet for the specific chip.
  • Page 45: Detailed I/O Memory Maps

    Memory Maps Detailed I/O Memory Maps The following tables provide detailed memory maps for the VMEchip2, MCchip, the MCECC memory controller chip, the Zilog Z85230, the Intel 82596CA controller, the NCR 53C710 controller, the IPIC chip, and the MK48T08 BBRAM/TOD Clock. Tables X-X - XX define the programming model for the Local Control and Status Registers (LCSR) in the VMEchip2.
  • Page 46: Table 1-6. Vmechip2 Memory Map - Lcsr Summary (Sheet 1 Of 2)

    Board Level Hardware Description Table 1-6. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: SLAVE ENDING ADDRESS 1 SLAVE ENDING ADDRESS 2 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER PRGM DATA...
  • Page 47 Memory Maps SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER PRGM DATA MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST...
  • Page 48 Board Level Hardware Description Table 1-6. VMEchip2 Memory Map - LCSR Summary (Sheet 2 of 2) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: BGTO GLOBAL TIME OFF TIME ON TIMER TICK TIMER 1 TICK TIMER 1 TICK TIMER 2 TICK TIMER 2 SCON PURS FAIL...
  • Page 49 Memory Maps LOCAL PRESCALER ACCESS TIME OUT CLOCK ADJUST TIMER TIMER SELECT COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW OVERFLOW COUNTER 2 COUNTER 1 SCALER SPARE IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 P ERROR IRQ1E TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL...
  • Page 50: Table 1-7. Mcchip Register Map

    Board Level Hardware Description Table 1-7. MCchip Register Map MCchip Base Address = $FFF42000 Offset D31-D24 D23-D16 D15-D8 D7-D0 MCchip ID MCchip Revision General Control Interrupt Vector Base Register Tick Timer 1 Compare Register Tick Timer 1 Counter Register Tick Timer 2 Compare Register Tick Timer 2 Counter Register LSB Prescaler Prescaler Clock...
  • Page 51: Table 1-8. Mcecc Internal Register Memory Map

    Memory Maps Table 1-8. MCECC Internal Register Memory Map MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Register Bit Names Offset Name CHIP ID CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 CHIP REVISION REV7 REV6 REV5 REV4 REV3 REV2 REV1...
  • Page 52 Board Level Hardware Description Table 1-8. MCECC Internal Register Memory Map (Continued) MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Register Bit Names Offset Name SCRUB TIMER SCRUB ADDR SAC26 SAC25 SAC24 CNTRL SCRUB ADDR SAC23 SAC22 SAC21 SAC20 SAC19 SAC18...
  • Page 53: Table 1-9. Z85230 Scc Register Addresses

    Memory Maps Table 1-9. Z85230 SCC Register Addresses SCC Register Address SCC #1 Port B Control $FFF45001 Port B Data $FFF45003 Port A Control $FFF45005 Port A Data $FFF45007 SCC #2 Port B Control $FFF45801 Port B Data $FFF45803 Port A Control $FFF45805 Port A Data $FFF45807...
  • Page 54: Table 1-11. 53C710 Scsi Memory Map

    Board Level Hardware Description Table 1-11. 53C710 SCSI Memory Map 53C710 Register Address Map Base Address is $FFF47000 Big Endian SCRIPTs Mode and Little Endian Mode SIEN SDID SCNTL1 SCNTL0 SOCL SODL SXFER SCID SBCL SBDL SIDL SFBR SSTAT2 SSTAT1 SSTAT0 DSTAT CTEST3...
  • Page 55: Ipic Overall Memory Map

    Memory Maps IPIC Overall Memory Map The following memory map table includes all devices selected by the IPIC map decoder. Note The IPIC chip on the MVME162LX supports up to four IndustryPack (IP) interfaces, designated IP_a through IP_d. The controller itself accommodates two IPs: IP_a and IP_b. In the maps that follow, the segments applicable to IP_c and IP_d are not used in the controller.
  • Page 56: Table 1-13. Ipic Memory Map-Control And Status Registers

    Board Level Hardware Description Table 1-13 contains a summary of the IPIC CSR registers. The CSR registers can be accessed as bytes, words, or longwords; they should not be accessed as lines. They are shown in the table as bytes. Table 1-13.
  • Page 57: Table 1-14. Mk48T08 Bbram/Tod Clock Memory Map

    Memory Maps Table 1-13. IPIC Memory Map—Control and Status Registers (Continued) IPIC Base Address = $FFFBC000 Register Register Register Bit Names Offset Name IP_c INT0 CONTROL c0_PLTY c0_E/L* c0_INT c0_IEN c0_ICLR c0_IL2 c0_IL1 c0_IL0 IP_c INT1 CONTROL c1_PLTY c1_E/L* c1_INT c1_IEN c1_ICLR c1_IL2...
  • Page 58: Table 1-15. Bbram Configuration Area Memory Map

    Board Level Hardware Description Table 1-15. BBRAM Configuration Area Memory Map Address Range Description Size (Bytes) $FFFC1EF8 - $FFFC1EFB Version $FFFC1EFC - $FFFC1F07 Serial Number $FFFC1F08 - $FFFC1F17 Board ID $FFFC1F18 - $FFFC1F27 $FFFC1F28 - $FFFC1F2B Speed $FFFC1F2C - $FFFC1F31 Ethernet Address $FFFC1F32 - $FFFC1F33 Reserved...
  • Page 59: Table 1-16. Tod Clock Memory Map

    Memory Maps Table 1-16. TOD Clock Memory Map Data Bits Address Function $FFFC1FF8 CONTROL $FFFC1FF9 SECONDS $FFFC1FFA MINUTES $FFFC1FFB HOUR $FFFC1FFC $FFFC1FFD DATE $FFFC1FFE MONTH $FFFC1FFF YEAR Note W = Write BitR = Read BitS = Signbit ST = Stop BitFT = Frequency Testx = Unuse http://www.mcg.mot.com/literature...
  • Page 60: Bbram, Tod Clock Memory Map

    (TOD) clock, is defined by the chip hardware. The first area is reserved for user data. The second area is used by Motorola networking software. The third area is used by the operating system. The fourth area is used by the MVME162LX board debugger (162Bug).
  • Page 61 Memory Maps The fields are defined as follows: 1. Four bytes are reserved for the revision or version of this structure. This revision is stored in ASCII format, with the first two bytes being the major version numbers and the last two bytes being the minor version numbers.
  • Page 62 Board Level Hardware Description 8. Two bytes are reserved for the local SCSI ID. The SCSI ID is stored in ASCII format. 9. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the memory mezzanine board in ASCII format. This does not include the prefix.
  • Page 63: Interrupt Acknowledge Map

    Memory Maps 23. Eight bytes are reserved for the serial number, in ASCII format, assigned to the optional fourth IndustryPack d. 24. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the optional fourth IndustryPack d. 25.
  • Page 64: Software Initialization

    Board Level Hardware Description Software Initialization Most functions that have been done with switches or jumpers on other modules are done by setting control registers on the MVME162LX Embedded Controller. At power-up or reset, the PROMs that contain the 162Bug debugging package set up the default values of many of these registers.
  • Page 65: Emc Compliance

    Software Initialization Note The GCSR allows a VMEbus master to reset the local bus. This feature is very dangerous and should be used with caution. The local reset feature is a partial system reset, not a complete system reset such as powerup reset or SYSRESET*.
  • Page 66 Board Level Hardware Description 1-52 Computer Group Literature Center Web Site...
  • Page 67: Introduction

    2Hardware Preparation and Installation Introduction This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME162LX Embedded Controller. Unpacking Instructions If the shipping carton is damaged upon receipt, insist that the carrier’s agent be present during the unpacking and inspection of the equipment.
  • Page 68: System Controller Select Header (J1)

    Hardware Preparation and Installation Figure 2-1 shows the placement of the switches, PCB jumper headers, connectors, and LED indicators on the controller. The controller has been factory tested and is shipped with the factory jumper settings listed in the following sections. It operates with its required and factory-installed debug monitor, MVME162Bug (162Bug), with these factory jumper settings.
  • Page 69: Figure 2-1. Mvme162Lx Switch, Header, Connector, Fuse, And Led Locations

    Hardware Preparation MVME 162-2XX FAIL FUSES SCON ABORT RESET Figure 2-1. MVME162LX Switch, Header, Connector, Fuse, and LED Locations http://www.mcg.mot.com/literature...
  • Page 70: General-Purpose Readable Jumpers Header (J11)

    Hardware Preparation and Installation General-Purpose Readable Jumpers Header (J11) PCB header J11 provides eight readable jumpers. These jumpers can be read as a register (at $FFF4202D) in the MCchip LCSR. The bit values are read as a zero when the jumper is installed, and as a one when the jumper is removed.
  • Page 71: Eprom/Flash Configuration Header (J12)

    Hardware Preparation EPROM/Flash Configuration Header (J12) The MVME162LX Embedded Controller comes with 1 MB of flash memory and four EPROM sockets ready for the installation of EPROMs, which may be ordered separately. The EPROM locations are standard JEDEC 32-pin DIP sockets that accommodate four jumper-selectable densities (128 Kbit x 8;...
  • Page 72: Table 2-1. Eprom/Flash Mapping - 128K X 8 Eproms

    Hardware Preparation and Installation The next five tables show the address range for each EPROM socket in all five configurations. GPI 3 (J11 pins 7-8) is a control bit in the MCchip ASIC that allows reset code to be fetched either from flash memory or from EPROMs.
  • Page 73: Table 2-3. Eprom/Flash Mapping - 512K X 8 Eproms

    Hardware Preparation Table 2-3. EPROM/Flash Mapping - 512K x 8 EPROMs GPI 3 Address Range Device Accessed Removed $FF800000 - $FF87FFFF EPROM A (XU24) $FF880000 - $FF8FFFFF EPROM B (XU23) $FF900000 - $FF97FFFF EPROM C (XU22) $FF980000 - $FF9FFFFF EPROM D (XU21) $FFA00000 - $FFBFFFFF On-Board Flash Installed $FF800000 - $FF9FFFFF...
  • Page 74: Table 2-5. Eprom/Flash Mapping - 1M X 8 Eproms, On-Board Flash Disabled

    Hardware Preparation and Installation Table 2-5. EPROM/Flash Mapping - 1M x 8 EPROMs, On-Board Flash Disabled GPI 3 Address Range Device Accessed Removed $FF800000 - $FF8FFFFF EPROM A (XU24) $FF900000 - $FF9FFFFF EPROM B (XU23) $FFA00000 - $FFAFFFFF EPROM C (XU22) $FFB00000 - $FFBFFFFF EPROM D (XU21) Not used On-Board Flash...
  • Page 75: Sram Backup Power Source Select Headers (J13, J1)

    Hardware Preparation SRAM Backup Power Source Select Headers (J13, J1) Jumper header J13 determines the source for onboard static RAM backup power on the controller’s PCB. Header J1 determines the source for backup power on the 2MB SRAM mezzanine board (if installed). The following backup power configurations are available for onboard SRAM through header J13.
  • Page 76: Scsi Terminator Enable Header (J14)

    Hardware Preparation and Installation The following backup power configurations are available for the 2MB mezzanine SRAM through header J1 (located on the mezzanine). In the factory configuration, the onboard battery serves as secondary power source. Removing the jumper may temporarily disable the SRAM Caution mezzanine.
  • Page 77: Memory Mezzanine Options

    Hardware Preparation Memory Mezzanine Options Two 100-pin connectors (J15 and J16) are provided on the controller’s main module to accommodate optional memory mezzanine boards. The following memory mezzanine options are available: 4 MB or 8 MB ECC DRAM (stackable on top) 16 MB or 32 MB ECC DRAM The mezzanine boards may either be used individually or be combined in a stack (not more than two deep).
  • Page 78: Installation Instructions

    – Connect user-supplied 50-pin cables to J3 and J4 as needed. Because of the varying requirements for each different kind of IP, Motorola does not supply these cables. – Bring the IP cables out the narrow slot in the controller’s front panel and attach them to the appropriate external equipment, depending on the nature of the particular IP(s).
  • Page 79: Mvme162Lx Module Installation

    Installation Instructions MVME162LX Module Installation With EPROMs and IndustryPacks installed and the controller’s headers properly configured, proceed as follows to install the controller in the VME chassis: 1. Turn all equipment power OFF and disconnect the power cable from the AC power source. Dangerous voltages, capable of causing death, are present in this equipment.
  • Page 80: System Considerations

    EIA-232-D serial ports, SCSI port, and LAN Ethernet port. – Note that some cables are not provided with the MVME162LX module and must be made or purchased by the user (Motorola recommends shielded cable for all peripheral connections to minimize radiation).
  • Page 81 Installation Instructions If the MVME162LX tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME162LX waits forever for the VMEbus cycle to complete. This will cause the system to lock up. There is only one situation in which the system might lack this global bus timeout: when the MVME162LX is not the system controller and there is no global bus timeout elsewhere in the system.
  • Page 82: Figure 2-2. Db25-Dte-To-Rj45 Adapter

    Hardware Preparation and Installation The controller uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals as well as the TXD and RXD transmit/receive data signals. Because the serial clocks are omitted in the controller’s implementation, serial communications are strictly asynchronous.
  • Page 83: Figure 2-3. Db25-Dce-To-Rj45 Adapter

    Installation Instructions Figure 2-3 shows the pin assignments required in a cable to adapt a DB25 DCE device to the RJ45 connectors. DB25 DCE DEVICE RJ45 JACK Figure 2-3. DB25-DCE-to-RJ45 Adapter Figure 2-4 diagrams the pin assignments required in a typical eight- conductor serial cable having RJ45 connectors at both ends.
  • Page 84 Hardware Preparation and Installation 2-18 Computer Group Literature Center Web Site...
  • Page 85: Overview

    3Debugger General Information Overview This chapter describes the basic features of the debugger used on the MVME162LX Embedded Controller. The firmware is known as the MVME162Bug 162Bug includes diagnostics for testing " " or simply the " ". It and configuring Industry Pack (IP) modules. Description of 162Bug The162Bug is a powerful evaluation and debugging tool for systems built around the MVME162LX CISC-based microcomputers.
  • Page 86: 162Bug Implementation

    (e.g., "GO"), then control may or may not return to the162Bug, depending on the outcome of the user’s program. If you have used one or more of Motorola's other debugging packages, you will find the CISC 162Bug very similar. Some effort has also been made to make the interactive commands more consistent.
  • Page 87: Installation And Start-Up

    Installation and Start-up Installation and Start-up Even though the 162Bug is installed on the MVME162LX Embedded Controller, you must follow the steps listed below in order for the 162Bug to operate properly with the controller. To prevent damage to the controller’s components, do not insert or remove the controller while power is applied.
  • Page 88 Debugger General Information J11 Pins Description Bit #0 (GPI0) When this bit is a one (high), it instructs the debugger to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.). Bit #1 (GPI1) When this bit is a one (high), it instructs the debugger to use the default setup/operation parameters in flash memory or ROM versus the user setup/operation parameters in Non- Volatile RAM (NVRAM).
  • Page 89 Installation and Start-up 4. Connect the terminal that is to be used as the 162Bug system console to the default debug EIA-232-D port at serial port 1 on the front panel of the controller. Refer to Chapter 2 for other connection options.
  • Page 90: Autoboot

    Debugger General Information Note This product contains a Real Time Clock (RTC) device on board. The device is backed up with a self-contained battery. Before shipment of the controller, the RTC device was stopped to preserve battery life. The board’s “Self-Tests” (ST)and operating systems require that the RTC be operating.
  • Page 91: Romboot

    As shipped from the factory, the 162Bug occupies an EPROM installed in socket XU24. This leaves three sockets (XU21 - XU23) and the flash available for your use. Contact your Motorola sales office for assistance. This function is configured/enabled by the Environment (ENV) command...
  • Page 92: Network Boot

    For complete details on how to use ROMboot, refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual. Network Boot Network Auto Boot is a software routine contained in the 162Bug Flash/PROM that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device.
  • Page 93: Restarting The System

    Restarting the System Restarting the System You can initialize the system to a known state in three different ways: reset, abort, and break. Each has characteristics which make it more appropriate than the others in certain situations. The debugger has a special feature upon a reset condition. This feature is activated by depressing the RESET and ABORT switches at the same time.
  • Page 94: Abort

    Debugger General Information Abort Abort is invoked by pressing and releasing the ABORT switch on the controller’s front panel. Whenever Abort is invoked when executing a user program (running target code), a "snapshot" of the processor state is captured and stored in the target registers. For this reason, abort is most appropriate when terminating a user program that is being debugged.
  • Page 95: Mpu Clock Speed Calculation

    Memory Requirements After debugger initialization is done and none of the above situations have occurred, the SYSFAIL* line is negated. This indicates to the user or VMEbus masters the state of the debugger. In a multi-computer configuration, other VMEbus masters could view the pertinent control and status registers to determine which CPU is asserting SYSFAIL*.
  • Page 96: Terminal Input/Output Control

    Debugger General Information The 162Bug requires 2KB of NVRAM for storage of board configuration, communication, and booting parameters. This storage area begins at $FFFC16F8 and ends at $FFFC1EF7. The 162Bug also requires a minimum of 64KB of contiguous read/write memory to operate. The ENV command controls where this block of memory is located.
  • Page 97: Disk I/O Support

    Disk I/O Support When observing output from any 162Bug command, the XON and XOFF characters which are in effect for the terminal port may be entered to control the output, if the XON/XOFF protocol is enabled (default). These characters are initialized to ^S and ^Q respectively by 162Bug, but you may change them with the PF command.
  • Page 98: Device Probe Function

    Disk I/O via 162Bug Commands These following 162Bug commands are provided for disk I/O. Detailed instructions for their use are found in the Debugging Package for Motorola 68K CISC CPUs User’s Manual. When a command is issued to a particular...
  • Page 99: Iop (Physical I/O To Disk)

    Disk I/O Support IOP (Physical I/O to Disk) IOP allows you to read or write blocks of data, or to format the specified device in a certain way. IOP creates a command packet from the arguments you have specified, and then invokes the proper system call function to carry out the operation.
  • Page 100 Refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual for information on using the above and other system calls. To perform a disk operation, the 162Bug must eventually present a...
  • Page 101: Default 162Bug Controller And Device Parameters

    Disk I/O Support Default 162Bug Controller and Device Parameters The 162Bug initializes the parameter tables for a default configuration of controllers and devices (refer to Appendix B). If the system needs to be configured differently than this default configuration (for example, to use a 70MB Winchester drive where the default is a 40MB Winchester drive), then these tables must be changed.
  • Page 102: Network I/O Support

    Debugger General Information Network I/O Support The Network Boot Firmware provides the capability to boot the CPU through the Flash/PROM debugger using a network (local Ethernet interface) as the boot device. The booting process is executed in two distinct phases. 1.
  • Page 103: Rarp/Arp Protocol Modules

    Network I/O Support RARP/ARP Protocol Modules The Reverse Address Resolution Protocol (RARP) consists of an identity- less node broadcasting a "whoami" packet onto the Ethernet, and waiting for an answer. The RARP server fills an Ethernet reply packet up with the target’s Internet Address and sends it.
  • Page 104: Multiprocessor Support

    Debugger General Information Multiprocessor Support The MVME162LX Embedded Controller dual-port RAM feature makes the shared RAM available to remote processors as well as to the local processor. This can be done by either of the following two methods. Either method can be enabled/disabled by the ENV command as its Remote Start Switch Method (refer to Appendix A).
  • Page 105 Multiprocessor Support The status codes that may be set by the bus master are: ASCII G (HEX 47) Use Go Direct (GD) logic specifying the MPAR address. ASCII B (HEX 42) Install breakpoints using the Go (G) logic. The Multiprocessor Address Register (MPAR), located in shared RAM location of $804 offset from the base address the debugger loads it at, contains the second of two longwords used to control communication between processors.
  • Page 106: Gcsr Method

    Debugger General Information If the code being executed in dual-port RAM is to reenter the debug monitor, a TRAP #15 call using function $0063 (SYSCALL .RETURN) returns control to the monitor with a new display prompt. Note that every time the debug monitor returns to the prompt, an R is moved into the MPCR to indicate that control can be transferred once again to a specified RAM location.
  • Page 107: Diagnostic Facilities

    Diagnostic Facilities Diagnostic Facilities The 162Bug package includes a set of hardware diagnostics for testing and troubleshooting the MVME162LX Embedded Controller. To use the diagnostics, switch directories to the diagnostic directory. If you are in the debugger directory, you can switch to the diagnostic directory with the Switch Directories (SD) command.
  • Page 108 Debugger General Information 3-24 Computer Group Literature Center Web Site...
  • Page 109: Entering Debugger Command Lines

    4Using The 162Bug Debugger Entering Debugger Command Lines 162Bug is command-driven and performs its various operations in response to user commands entered at the keyboard. When the debugger prompt ( ) appears on the terminal screen, the debugger is ready 162-Bug>...
  • Page 110: Syntactic Variables

    Using The 162Bug Debugger The commands are shown using a modified Backus-Naur form syntax. The metasymbols used are: boldface strings A boldface string is a literal such as a command or a program name, and is to be typed just as it appears. italic strings An italic string is a "syntactic variable"...
  • Page 111: Expression As A Parameter

    Entering Debugger Command Lines Expression as a Parameter An expression can be one or more numeric values separated by the arithmetic operators: plus (+), minus (-), multiplied by (*), divided by (/), logical AND (&), shift left (<<), or shift right (>>). Numeric values may be expressed in either hexadecimal, decimal, octal, or binary by immediately preceding them with the proper base identifier.
  • Page 112: Address As A Parameter

    Using The 162Bug Debugger Valid expression examples: Expression Result (In Hex) Notes FF0011 FF0011 45+99 &45+&99 @35+@67+@10 %10011110+%1001 88<<4 shift left AA&F0 logical AND The total value of the expression must be between 0 and $FFFFFFFF. Address as a Parameter Many commands use ADDR as a parameter.
  • Page 113: Table 4-1. Debugger Address Parameter Formats

    Entering Debugger Command Lines Table 4-1. Debugger Address Parameter Formats Format Example Description Absolute address+contents of automatic offset register. N+Rn 130+R5 Absolute address+contents of the specified offset register (not an assembler-accepted syntax). (An) (A1) Address register indirect. (also postincrement, predecrement) (d,An) or (120,A1) Address register indirect with...
  • Page 114: Offset Registers

    Using The 162Bug Debugger Note In commands with RANGE specified as ADDR DEL ADDR, and with size option W or L chosen, data at the second (ending) address is acted on only if the second address is a proper boundary for a word or longword, respectively. Offset Registers Eight pseudo-registers (R0 through R7) called offset registers are used to simplify the debugging of relocatable and position-independent modules.
  • Page 115 Entering Debugger Command Lines Example: A portion of the listing file of an assembled, relocatable module is shown below: * MOVE STRING SUBROUTINE 0 00000000 48E78080 MOVESTR MOVEM.L D0/A0,—(A7) 0 00000004 4280 CLR.L 0 00000006 1018 MOVE.B (A0)+,D0 0 00000008 5340 SUBQ.W #1,D0 0 0000000A 12D8...
  • Page 116: Port Numbers

    00014+R0 4E75 162Bug> For additional information about the offset registers, refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual. Port Numbers Some 162Bug commands give you the option to choose the port to be used to input or output. Valid port numbers which may be used for these commands are as follows: 1.
  • Page 117: Entering And Debugging Programs

    After each source line is entered, it is assembled and the object code is loaded to memory. Refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual for complete details of the 162Bug Assembler/Disassembler.
  • Page 118: Preserving The Debugger Operating Environment

    Using The 162Bug Debugger Preserving the Debugger Operating Environment This section explains how to avoid contaminating the operating environment of the debugger. 162Bug uses certain of the MVME162LX onboard resources and also offboard system memory to contain temporary variables and exception vectors. If you disturb resources upon which 162Bug depends, then the debugger may function unreliably or not at all.
  • Page 119: Hardware Functions

    Preserving the Debugger Operating Environment Hardware Functions The only hardware resources used by the debugger are the EIA-232-D ports, which are initialized to interface to the debug terminal. If these ports are reprogrammed, the terminal characteristics must be modified to suit, or the ports should be restored to the debugger-set characteristics prior to reinvoking the debugger.
  • Page 120: Using 162Bug Target Vector Table

    Using The 162Bug Debugger Example: Trace one instruction using debugger. 162Bug> =00010000 SR =2700=TR:OFF_S._7_..=00000000 =0000DFFC MSP =0000EFFC ISP* =0000FFFC SFC =0=F0 =0=F0 CACR =0=..=00000000 D1 =00000000 D2 =00000000 D3 =00000000 =00000000 D5 =00000000 D6 =00000000 D7 =00000000 =00000000 A1 =00000000 A2 =00000000 A3 =00000000...
  • Page 121: Creating A New Vector Table

    Preserving the Debugger Operating Environment The 162Bug initializes the target vector table with the debugger vectors listed in Table 4-2 and fills the other vector locations with the address of a generalized exception handler (refer to the 162Bug Generalized Exception Handler section in this chapter).
  • Page 122 Using The 162Bug Debugger The following is an example of a routine which builds a separate vector table and then moves the VBR to point at it: BUILDX - Build exception vector table **** BUILDX MOVEC.L VBR,A0 Get copy of VBR. $10000,A1 New vectors at $10000.
  • Page 123: 162Bug Generalized Exception Handler

    Preserving the Debugger Operating Environment The following is an example of an exception handler which can pass an exception along to the debugger: EXCEPT - Exception handler **** EXCEPT SUBQ.L #4,A7 Save space in stack for a PC value. LINK A6,#0 Frame pointer for accessing PC space.
  • Page 124 Using The 162Bug Debugger 162Bug> =00010000 SR =2708=TR:OFF_S._7_.N... =00000000 =0000DFFC MSP =0000EFFC ISP* =0000FFFC SFC =0=F0 =0=F0 CACR =0=..=00000001 D1 =00000001 D2 =00000000 D3 =00000000 =00000000 D5 =00000002 D6 =00000000 D7 =00000000 =00000000 A1 =00000000 A2 =00000000 A3 =00000000 =00000000 A5 =00000000 A6 =00000000 A7...
  • Page 125: Floating Point Support

    Floating Point Support Floating Point Support The floating point unit (FPU) of the MC68040 microprocessor chip is supported in the 162Bug. For MVME162Bug, the commands MD, MM, RM, and RS have been extended to allow display and modification of floating point data in registers and in memory. Floating point instructions can be assembled/disassembled with the DI option of the MD and MM commands.
  • Page 126: Single Precision Real

    Using The 162Bug Debugger Single Precision Real This format would appear in memory as: 1-bit sign field (1 binary digit) 8-bit biased exponent field (2 hex digits. Bias = $7F) 23-bit fraction field (6 hex digits) A single precision number takes 4 bytes in memory. Double Precision Real This format would appear in memory as: 1-bit sign field...
  • Page 127: Packed Decimal Real

    Floating Point Support Packed Decimal Real This format would appear in memory as: 4-bit sign field (4 binary digits) 16-bit exponent field (4 hex digits) 68-bit mantissa field (17 hex digits) A packed decimal number takes 12 bytes in memory. Scientific Notation This format provides a convenient way to enter and display a floating point decimal number.
  • Page 128: The 162Bug Debugger Command Set

    The CNFG and ENV commands are explained in Chapter 5. Controllers, devices, and their LUNs are listed in Appendix B or Appendix C. All other command details are explained in the Debugging Package for Motorola 68K CISC CPUs User’s Manual.
  • Page 129 The 162Bug Debugger Command Set Table 4-3. Debugger Commands (Continued) Command Command Line Mnemonic Title Syntax Block of Memory BS RANGE DEL TEXT [;B|W|L] Search or BS RANGE DEL data [DEL mask] [;B|W|L [,N][,V]] Block of Memory BV RANGE DEL data [increment] [;B|W|L] Verify Concurrent Mode CM [[PORT][DEL ID-STRING]...
  • Page 130 Using The 162Bug Debugger Table 4-3. Debugger Commands (Continued) Command Command Line Mnemonic Title Syntax I/O Inquiry IOI [;[C|L]] I/O Physical (Direct Disk Access) I/O "TEACH" for IOT [;[A][F][H][T]] Configuring Disk Controller IRQM Interrupt Request Mask IRQM [MASK] Load S-records from LO [n] [ADDR] [;X|C|T] [=text] Host Macro Define/Display...
  • Page 131 The 162Bug Debugger Command Set Table 4-3. Debugger Commands (Continued) Command Command Line Mnemonic Title Syntax Automatic Network Boot Operating System Network Boot NBH [Controller LUN][Device LUN] Operating System and [Client IP Address][Server IP Address][String] Halt Network Boot NBO [Controller LUN][Device LUN] Operating System [Client IP Address][Server IP Address][String] NIOC...
  • Page 132 Using The 162Bug Debugger Table 4-3. Debugger Commands (Continued) Command Command Line Mnemonic Title Syntax REMOTE Connect the Remote REMOTE Modem to CSO RESET Cold/Warm Reset RESET Read Loop RL ADDR;[B|W|L] Register Modify RM [REG] [;[S|D]] Register Set RS REG [DEL EXP|DEL ADDR][;[S|D]] Switch Directories Set Time and Date SET mmddyyhhmm -or- SET n;C...
  • Page 133: Configure Board Information Block

    AConfigure and Environment Commands Configure Board Information Block CNFG [;[I][M]] This command is used to display and configure the board information block. This block is resident within the Non-Volatile RAM (NVRAM). Refer to the MVME162LX Embedded Controller Programmer’s Reference Guide for the actual location. The information block contains various elements detailing specific operation parameters of the hardware.
  • Page 134 Configure Board Information Block ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " " ECC Memory Mezzanine #2 (PWA) Serial Number = " " Serial Port 2 Personality Artwork (PWA) Identifier = " " Serial Port 2 Personality Module (PWA) Serial Number = " "...
  • Page 135: Set Environment To Bug/Operating System

    Configure and Environment Commands Set Environment to Bug/Operating System ENV [;[D]] The ENV command allows you to interactively view/configure all Bug operational parameters that are kept in Battery Backed Up RAM (BBRAM), also known as Non-Volatile RAM (NVRAM). The operational parameters are saved in NVRAM and used whenever power is lost.
  • Page 136: Table A-1. Env Command Parameters

    Set Environment to Bug/Operating System Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default Bug or System environment [B/S] Bug mode Field Service Menu Enable [Y/N] Do not display field service menu. Remote Start Method Switch Use both the Global Control and Status [G/M/B/N] Register (GCSR) in the VMEchip2, and the...
  • Page 137 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Auto Boot at power-up only Auto Boot is attempted at power up reset only. [Y/N] Auto Boot Controller LUN LUN of a disk/tape controller module currently supported by the Bug.
  • Page 138 Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default ROM Boot Abort Delay This is the time in seconds that the ROMboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the Break key.
  • Page 139 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Network Autoboot Configuration 00000000 This is the address where the network interface Parameters Pointer (NVRAM) configuration parameters are to be saved/retained in NVRAM; these parameters are the necessary parameters to perform an unattended network boot.
  • Page 140 Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Memory Search Delay Enable There will be no delay before the Bug begins [Y/N] its search for a work page. Memory Search Delay Address FFFFD20F Default address is $FFFFD20F.
  • Page 141 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Memory Configuration Defaults: The default configuration for Dynamic RAM mezzanine boards will position the mezzanine with the largest memory size to start at the address selected with the "ENV" parameter "Base Address of Dynamic Memory".
  • Page 142 Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default ENV asks the following series of questions to set up the VMEbus interface for the MVME162LX Embedded Controller. You should have a working knowledge of the VMEchip2 as given in the MVME162LX Embedded Controller Programmer’s Reference Guide in order to perform this configuration.
  • Page 143 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Slave Enable #2 [Y/N] Do not setup and enable the Slave Address Decoder #2. Slave Starting Address #2 00000000 Base address of the local resource that is accessible by the VMEbus.
  • Page 144 Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Control #1 Defines the access characteristics for the address space defined with this master address decoder. Default is $0D. Master Enable #2 [Y/N] Do not setup and enable the Master Address Decoder #2.
  • Page 145 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Ending Address #3 00000000 Ending address of the VMEbus resource that is accessible from the local bus. If enabled, the default is $00FFFFFF, otherwise $00000000. Master Control #3 Defines the access characteristics for the address space defined with this master address...
  • Page 146 Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Short I/O (VMEbus A16) Enable Yes, Enable the Short I/O Address Decoder. [Y/N] Short I/O (VMEbus A16) Control Defines the access characteristics for the address space defined with the Short I/O address decoder.
  • Page 147 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default VMEC2 GCSR Board Base Specifies the base address ($FFFFD2XX) in Address Short I/O for this board. Default = $00. VMEbus Global Time Out Code This controls the VMEbus timeout when the MVME162LX is systems controller.
  • Page 148: Configuring The Industrypacks

    Set Environment to Bug/Operating System Configuring the IndustryPacks asks the following series of questions to set up IndustryPacks (IPs) on MVME162LX Embedded Controllers. The MVME162LX Embedded Controller Programmer’s Reference Guide describes the base addresses and the IP register settings. Refer to that manual for information on setting base addresses and register bits.
  • Page 149 Configure and Environment Commands IP D/C/B/A General Control = 00000000? Define the general control requirements for the IP modules: Bits Register Address 31-24 FFFBC01B 23-16 FFFBC01A 15-08 FFFBC019 07-00 FFFBC018 IP D/C/B/A Interrupt 0 Control = 00000000? Define the interrupt control requirements for the IP modules channel 0: Bits Register Address 31-24...
  • Page 150 Set Environment to Bug/Operating System Before environment parameters are saved in the NVRAM, Caution a warning message will appear if the user has specified environment parameters which will cause an overlap condition. The important information about each configurable element in the memory map is displayed, showing where any overlap conditions exist.
  • Page 151: Disk/Tape Controller Modules Supported

    BDisk/Tape Controller Data Disk/Tape Controller Modules Supported Note The controllers listed below have been discontinued as of the publication date of this manual. The information contained in this appendix is provided for customers that may have ordered these controllers prior to the discontinuance date. The following VMEbus disk/tape controller modules are supported by the 162Bug.
  • Page 152: Disk/Tape Controller Default Configurations

    Disk/Tape Controller Default Configurations Disk/Tape Controller Default Configurations Note SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group. CISC Embedded Controllers -- 7 Devices Controller LUN Address Device LUN Device Type $XXXXXXXX SCSI Common Command Set...
  • Page 153 Disk/Tape Controller Data MVME323 -- 4 Devices Controller LUN Address Device LUN Device Type $FFFFA000 ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive $FFFFA200 ESDI Winchester hard drive MVME327A -- 9 Devices Controller LUN Address Device LUN Device Type $FFFFA600 SCSI Common Command Set...
  • Page 154 Disk/Tape Controller Default Configurations MVME328 -- 14 Devices Controller LUN Address Device LUN Device Type $FFFF9000 SCSI Common Command Set (CCS), which may be any of these: - Removable flexible direct access (TEAC style) $FFFF9800 - CD-ROM - Sequential access $FFFF4800 Same as above, but these will only be available if...
  • Page 155: Iot Command Parameters For Supported Floppy Types

    Disk/Tape Controller Data IOT Command Parameters for Supported Floppy Types The following table lists the proper command parameters for floppies used with boards such as the MVME328 and MVME162LX. Floppy Types and Formats IOT Parameter DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT Sector Size 0- 128 1- 256 2- 512 3-1024 4-2048 5-4096 =...
  • Page 156 IOT Command Parameters for Supported Floppy Types Computer Group Literature Center Web Site...
  • Page 157: Network Controller Modules Supported

    CNetwork Controller Data Network Controller Modules Supported The following VMEbus network controller modules are supported by the MVME162Bug. The default address for each type and position is showed to indicate where the controller must reside to be supported by the MVME162Bug.
  • Page 158 Computer Group Literature Center Web Site...
  • Page 159: Eia-232-D Interconnections

    DSerial Interface Connections EIA-232-D Interconnections Connector J17 houses the four RJ45 sockets on the MVME162LX Embedded Controller’s front panel which provide the serial interface connections. Table D-1 lists the pin numbers, signal mnemonics, and signal descriptions for the RJ45 connectors. The signals are identical for each serial port.
  • Page 160: Figure D-1. Serial Interface Connections

    EIA-232-D Interconnections The MVME162LX Embedded Controller uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals as well as the TXD and RXD transmit/receive data signals. Because the serial clocks are omitted in the MVME162LX implementation, serial communications are strictly asynchronous.
  • Page 161: Figure D-2. Db25-Dte-To-Rj45 Adapter

    Serial Interface Connections Figure D-2 shows the pin assignments required in a cable to adapt a DB25 DTE device to the RJ45 connectors. DB25 DTE DEVICE RJ45 JACK Figure D-2. DB25-DTE-to-RJ45 Adapter Figure D-3 shows the pin assignments required in a cable to adapt a DB25 DCE device to the RJ45 connectors.
  • Page 162: Figure D-4. Typical Rj45 Serial Cable

    EIA-232-D Interconnections Figure D-4 shows the pin assignments required in a typical eight- conductor serial cable having RJ45 connectors at both ends. Note that all wires are crossed. RJ45 CONNECTOR RJ45 CONNECTOR Figure D-4. Typical RJ45 Serial Cable Computer Group Literature Center Web Site...
  • Page 163: Ethernet Interconnections

    ENetwork Port Connections Ethernet Interconnections Connector J9 is a 15-pin socket connector mounted on the front panel. It provides the Ethernet LAN (Local Area Network) port connections for the MVME162LX Embedded Controller. Table E-1 lists the pin numbers, signal mnemonics, and signal descriptions for J9. Table E-1.
  • Page 164 Ethernet Interconnections Computer Group Literature Center Web Site...
  • Page 165: Scsi Interconnections

    FSCSI Bus Connections SCSI Interconnections Connector J10 is a 68-pin socket connector mounted on the front panel. It provides the Small Computer System Interface (SCSI) I/O bus connections. Table F-1 lists the pin numbers, signal mnemonics, and signal descriptions for J10. Table F-1.
  • Page 166 SCSI Interconnections Table F-1. SCSI Connector J10 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic BSY* Busy. SCSI busy signal; indicates that the bus is in use. ACK* Acknowledge. Driven by an initiator; indicates an acknowledgment for a REQ/ACK data transfer handshake. RST* Reset.
  • Page 167: Mezzanine Connector J15 Signals

    GMezzanine Board Connectors Mezzanine Connector J15 Signals Connector J15 is a standard double-row 100-pin socket connector mounted on the MVME162LX Embedded Controller PWB (see Figure 2-1). It connects to a corresponding 100-pin plug connector on the ECC DRAM mezzanine board and (together with J16) carries the DRAM address, data, and control signals to and from the mezzanine board.
  • Page 168 Mezzanine Connector J15 Signals Table G-1. Mezzanine Connector J15 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction LTA* Bidirectional Local Transfer Acknowledge. MC68040 transfer acknowledge. LSIZ0 Bidirectional Local Transfer Size 0. MC68040 transfer size attribute. Ground. LSIZ1 Bidirectional Local Transfer Size 1.
  • Page 169 Mezzanine Board Connectors Table G-1. Mezzanine Connector J15 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction LSC0 Bidirectional Local Snoop Control 0. MC68040 snoop control attribute. MEZZIPL0* Output Mezzanine Interrupt Line 0. Encoded interrupt line from mezzanine. LSC1 Bidirectional Local Snoop Control 1.
  • Page 170 Mezzanine Connector J15 Signals Table G-1. Mezzanine Connector J15 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction PEIRQ* Output Parity Error Interrupt Request. Issued to VMEchip from mezzanine. SRAMSIZ0 Output SRAM Size 0. Encoded SRAM size. Reserved.
  • Page 171 Mezzanine Board Connectors Table G-1. Mezzanine Connector J15 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction Ground. 76-79 LA<19>- Bidirectional Local Address bus (bits 19-22). MC68040 LA<22> address lines. Ground. 81, 82 LA<24>, Bidirectional Local Address bus (bits 24, 23). MC68040 LA<23>...
  • Page 172: Mezzanine Connector J16 Signals

    Mezzanine Connector J16 Signals Mezzanine Connector J16 Signals Connector J16 is a standard double-row 100-pin socket connector mounted on the MVME162LX Embedded Controller PWB (see Figure 2-1). It connects to a corresponding 100-pin plug connector on the ECC DRAM mezzanine board and (together with J15) carries the DRAM address, data, and control signals to and from the mezzanine board.
  • Page 173 Mezzanine Board Connectors Table G-2. Mezzanine Connector J16 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction Ground. 23, 24 LD<16>, Bidirectional Local Data bus (bits 16, 17). MC68040 data LD<17> lines. Ground. 26, 27 LD<19>, Bidirectional Local Data bus (bits 19, 18). MC68040 data LD<18>...
  • Page 174 Mezzanine Connector J16 Signals Table G-2. Mezzanine Connector J16 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction Ground. DRAM_PD2 Bidirectional DRAM Parity Data (bit 2). MEZ0 Output Mezzanine 0. Encoded DRAM size from mezzanine. DRAM_PD3 Bidirectional DRAM Parity Data (bit 3). Bit 3 is the most significant bit.
  • Page 175 Mezzanine Board Connectors Table G-2. Mezzanine Connector J16 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction RDRAM_A8 Input DRAM Address (bit 8). Parity DRAM row/column address line. Ground. RDRAM_A9 Input DRAM Address (bit 9). Parity DRAM row/column address line.
  • Page 176 Mezzanine Connector J16 Signals Table G-2. Mezzanine Connector J16 Interconnect Signals (Continued) Signal Signal Signal Name and Description Number Mnemonic Direction Ground. DRAMWELM Input DRAM Write Enable (lines D15-D08). Parity DRAM write enable signal. DRAMWEUM Input DRAM Write Enable (lines D23-D16). Parity DRAM write enable signal.
  • Page 177: Mezzanine Board Dimensions

    Mezzanine Board Connectors Mezzanine Board Dimensions The following drawings specify the dimensions critical to connector and mounting hole placement on the mezzanine boards used with the MVME162LX Embedded Controller. They may be helpful in the event you wish to fabricate your own mezzanine boards for use with the controller.
  • Page 178 Mezzanine Board Dimensions 0.265 PIN 1 0.100 2 PL 0.185 BOTTOM CONNECTOR 0.084 2.475 0.125 2 PL 4.634 5.255 4.725 BOTTOM VIEW PIN 1 TOP CONNECTOR 3.011 3.025 3.400 Figure G-2. Mezzanine Board Dimensions (SRAM and ECC DRAM) G-12 Computer Group Literature Center Web Site...
  • Page 179: Solving Startup Problems

    HTroubleshooting CPU Boards Solving Startup Problems In the event of difficulty with your CPU board, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment (the board was tested under those conditions before it left the factory).
  • Page 180 Solving Startup Problems Table H-1. Troubleshooting MVME162LX Boards (Continued) Condition Possible Problem Try This: II. There is a A. The keyboard or Recheck the keyboard and/or mouse connections and power. display on the mouse may be terminal, but input connected from the keyboard incorrectly.
  • Page 181 Troubleshooting CPU Boards Table H-1. Troubleshooting MVME162LX Boards (Continued) Condition Possible Problem Try This: IV. Continued 2. At the command line prompt, type in: env;d <CR> This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y <CR>...
  • Page 182 Table H-1. Troubleshooting MVME162LX Boards (Continued) Condition Possible Problem Try This: V. The debugger is A. No apparent No further troubleshooting steps are required. in system mode and problems — the board troubleshooting is autoboots, or the done. board has passed selftests.
  • Page 183: Industrypack Logic Interface Interconnections

    IInput/Output Connections IndustryPack Logic Interface Interconnections For each IP module, there are two 50-pin plug connectors on the MVME162LX Embedded Controller: J5/J6 and J7/J8. Connectors J6 and J8 provide the IndustryPack logic interface. Connectors J5 and J7 are application specific and their definition is dependent upon which IP modules are used.
  • Page 184 IndustryPack Logic Interface Interconnections Table I-1. IndustryPack Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic 25, 26 Ground. Second and third of four ground pins. Serve as zero- volt reference for logic signals, and as return path for the power supplies furnishing operating voltages to the IndustryPack.
  • Page 185 Input/Output Connections Table I-1. IndustryPack Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic IOSel* I/O Select. Fourth of four ‘‘select’’ lines driven by the MVME162 to enable the IP. This line is used in executing input or output cycles. IOSel* is not bussed; the signal is unique to each IndustryPack.
  • Page 186: Industrypack I/O Interconnections

    IndustryPack I/O Interconnections Table I-1. IndustryPack Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic Address Line 6. One of six address lines; driven by the MVME162 to address I/O locations on the IndustryPack module designated by the four ‘‘select’’ lines. Ack* Data Acknowledge.
  • Page 187: Remote Reset/Led Interconnection

    Input/Output Connections Remote Reset/LED Interconnection Connector J2 provides the interconnection for the Remote Reset switch and LED. Table I-2 lists the pin numbers and signal mnemonics for connector J2. Table I-2. Remote Reset/LED interconnect Signals Signal Pin Number Mnemonic +5VF LAN LED +12V LED SCSI LED...
  • Page 188: Vme Bus Interconnection

    VME Bus Interconnection VME Bus Interconnection The MVME162LX PCB interconnects with the VMEbus through rows A, B, and C of backplane connector P1 and through row B of backplane connector P2. Connector P1 Interconnect Signals Connector P1 is a standard DIN 41612 triple-row, 96-pin male connector. The MVME162 interconnects with the VMEbus through rows A, B, and C of connector P1 and through row B of connector P2.
  • Page 189 Input/Output Connections Table I-3. Connector P1 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic DTACK* Data Transfer Acknowledge. An open-collector driven signal generated by a data transfer bus slave. The falling edge of this signal indicates that valid data is available on the data bus during a read cycle, or that data has been accepted from the data bus during a write cycle.
  • Page 190 VME Bus Interconnection Table I-3. Connector P1 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic ACFAIL* System AC Power Fail. An open-collector-driven signal which indicates that the AC input to the power supply is not being provided or the required input voltage level is not being met. BG0IN* Bus Grant In (level 0).
  • Page 191 Input/Output Connections Table I-3. Connector P1 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic C1-C8 D08-D15 Data Bus (bits 8-15). Eight of 16 three-state bidirectional data lines that provide the data path between the data transfer bus master and slave. Ground SYSFAIL* System Failure.
  • Page 192: Connector P2 Interconnect Signals

    VME Bus Interconnection Connector P2 Interconnect Signals Connector P2 is a standard DIN 41612 triple-row, 96-pin male connector. Each pin connection, signal mnemonic, and signal characteristic for the connector is listed in Table I-4. Table I-4. Connector P2 Interconnect Signals Signal Signal Name and Description Number...
  • Page 193 Input/Output Connections Table I-4. Connector P2 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic REQ* Request (SCSI). Signal driven by a target to indicate a request for a REQ/ACK data transfer handshake. O/I* Output/Input (SCSI). Signal driven by a target which controls the direction of data movement on the bus.
  • Page 194 VME Bus Interconnection Table I-4. Connector P2 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic TRXC4 EIA-232-D Transmit Clock (serial port 4). This line can be configured to clock output data to the modem from the terminal. CTS4 EIA-232-D Clear to Send (serial port 4).
  • Page 195 Input/Output Connections Table I-4. Connector P2 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic T– Transmit – (output), Ethernet. This line is intended to operate into terminated transmission lines. Transmit + (input), Ethernet. Part of a differential pair. R–...
  • Page 196 VME Bus Interconnection Table I-4. Connector P2 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic RTS1 EIA-232-D Request to Send (serial port 1). Input from modem to terminal when the modem is required to transmit a message. With RTS1 off, the modem carrier remains off. When RTS1 is turned on, the modem immediately turns on the carrier.
  • Page 197: Motorola Documentation

    The following publications are applicable to the MVME162LX and may provide additional reference information. You may download copies of this documentation in PDF and/or HTML format from the Motorola Computer Group’s World Wide Web site at http://www.mcg.mot.com/literature.
  • Page 198: Non-Motorola Documentation

    M68040UM M68000 Family Reference Manual M68000FR You may also purchase hard copies of these Motorola manuals in the following ways: 1. Through the Motorola Computer Group’s World Wide Web site. 2. (USA and Canada only) -- By contacting the Literature Center via phone or fax at the numbers listed under How to Order Literature at the Motorola Computer Group’s World Wide Web site.
  • Page 199: Support Information

    28F008SA Flash Memory Data Sheet, order number 2904351-001; Intel Literature Sales, P.O. Box 7641, Mt. Prospect, IL 60056-7641. Support Information You can obtain connector interconnect signal information, parts lists, and schematics for the MVME162LX Embedded Controller free of charge by contacting your local Motorola sales office. http://www.mcg.mot.com/literature...
  • Page 200 Computer Group Literature Center Web Site...
  • Page 201 Index Numerics serial port 1 4-8 stack 3-12 162Bug 2-2 syntactic variables 4-2 address system routines 4-9 as a parameter 4-4 using the debugger 4-1 formats 4-4 vector base register 4-11 parameter formats 4-5 vector table and workspace 4-10 addresses in command lines 4-4 vector tables 4-10 arithmetic expessions 4-3 27C040 EPROM 3-2...
  • Page 202 Index batteries 1-17 configure Battery Backed Up RAM (BBRAM) and BIB A-1 Clock 1-18, A-3 debug parameters A-3 BBRAM 1-18 configuring Configuration Area memory map 1-44 base addresses of IndustryPacks A-16 BG (bus grant) 2-14 IndustryPacks A-16 BH (bootstrap and halt) 3-15 IndustryPacks A-3 binary number 1-10 VMEbus interface A-10...
  • Page 203 directories examples switching 3-23 address formats 4-4 Disk I/O exception handler usage 4-15 error codes 3-17 exception vector 4-12 support 3-13 numeric value expression 4-3 via 162Bug Commands 3-14 relocatable module 4-7 via 162Bug system calls 3-15 valid expressions 4-4 disk/tape controller default configurations exception handler 4-15...
  • Page 204 Index Interrupt Stack Pointer (ISP) 3-12 interrupts 1-23 GCSR 2-15 IOC (I/O control) 3-15 board control register 1-51 IOI (input/output inquiry) 3-14 GPCSR0 A-8 IOP (physical I/O to disk) 3-15 method 3-22 IOT (I/O teach) 3-15 general-purpose readable jumpers header command parameters for supported (J11) 2-4 floppy types B-5...
  • Page 205 MVME162FX C-1 board-level hardware features 1-1 mantissa field (floating point data) 4-17 block diagram 1-11 manual terminology 1-10 models 1-3 manufacturers’ documents D-1 module installation 2-13 manufacturing test process 3-23 specifications 1-7 MC68040 or MC68LC040 MPU 1-14 switch, header, connector, fuse, and TRAP instructions 4-9 LED locations 2-3 MC68xx040 cache 1-14...
  • Page 206 Index specification J-2 termination 1-21 P1 connector 1-24 terminator configuration 1-21, 2-10 P2 connector 1-24, 4-8 terminator enable header (J14) 2-10 packed decimal real format 4-19 terminator power 1-22, 2-15 parity DRAM 2-11 SD command 3-23 port 1 or 01 4-8 sequential access device B-2, B-4 port number(s) 4-1, 4-8 serial...
  • Page 207 switching 3-23 VMEbus 1-19 syntactic variables, 162Bug 4-2 accesses to the local bus 1-49 SYSFAIL* assertion/negation 3-10 interface and VMEchip2 1-19 system memory map 1-49 calls 3-15 short I/O memory map 1-49 considerations 2-14 specification J-2 console 3-5 VMEchip2 1-19 controller function 3-4 GCSR 2-15, 3-22 controller select header (J1) 2-2...
  • Page 208 Index IN-8 Computer Group Literature Center Web Site...