Ddr Vtt Termination; Figure 103. Ddr Smrcomp Resistive Compensation; Figure 104. Smvswingl And Smvswingh Reference Voltage Generation Circuit - Intel 852GME Design Manual

R

Figure 103. DDR SMRCOMP Resistive Compensation

The GMCH's system memory resistive compensation mechanism also requires the generation of
reference voltages to the SMVSWINGL and SMVSWINGH pins with a value of 1/3*VCCP. The
schematic for SMVSWINGL and SMVSWINGH voltage generation is illustrated in
Figure 104. Two resistive dividers with R1a = R2b = 150
generate the SMVSWINGL and SMVSWINGH voltages. SMVSWINGL and SMVSWINGH
components should be placed within 0.5 inches of their respective pins and connected with a 15-mil
wide trace. To avoid coupling with any other signals, maintain a minimum of 25 mils of separation to
other signals.

Figure 104. SMVSWINGL and SMVSWINGH Reference Voltage Generation Circuit

0.1 µF
12.5.5.

DDR VTT Termination

The recommended topology for DDR-SDRAM Data, Control, and Command signal groups requires that
all these signals to be terminated to a 1.25-V source, VTT, at then end of the memory channel opposite
the GMCH. A solid 1.25-V termination island should be used to for this purpose. The VTT termination
island should be placed on the top signal layer, just beyond the last SO-DIMM connector and must be at
least 50-mils wide. The Data and Command signals should be terminated using one resistor per signal.
Resistor packs and ± 5% tolerant resistors are acceptable for this application. Only signals from the
same DDR signal group can share a resistor pack. See Section 12.5.1 and Section 12.7 for details on
high frequency and bulk decoupling requirements.
® ®
Intel 852GME, Intel 852GMV and Intel
60.4Ω +/- 1%
SMRCOMP
+VCCSM
R1a
150
SMVSWINGL
SMVSWiNGL
R2a
604
®
852PM Chipset Platforms Design Guide
Platform Power Delivery Guidelines
+V2.5
60.4Ω +/- 1%
± 1% and R1b = R2a = 604
SMVSWINGH
SMVSWiNGH
MCH/GMCH
0.1 µF
± 1%
+VCCSM
R1b
604
R2b
150
0.1 µF
223