I 2 C Post Code Headers; Table 20. J3A1 And J6C1 I C Post Code Headers; Figure 127. Main Board Jumper Locations; Post Code Headers - Intel SR6850HW4 - Server Platform - 0 MB RAM Product Manual

Name
BMC RESET
FWHID
2
I C POST Code Headers
The main board has a 5-pin header (with the fourth pin removed) for the I
headers are J3A1 on the I/O riser card and J6C1 on the memory board. The I
SMB bus in the Intel
3.3 V standby. Table 20 shows the pin assignments.
Table 20. J3A1 and J6C1 I
Pin
1
2
3
4
5
242
Location Default
J8C2 Stuff
Empty
J8C3 Stuff
Empty

Figure 127. Main Board Jumper Locations

®
82801EB I/O Controller Hub 5. The data and clock signals are pulled up to
2
C POST Code Headers
Signal
12 V Standby
SMBDATA
SMBCLK
NC – pin removed
Ground
Intel® Server Platforms SR6850HW4 and SR6850HW4/M Product Guide
Stuffed Jumper State
(Default in Bold)
1 – 2 = BMC enabled
2 – 3 = BMC Disabled
1-2 = Enables BMC controls FWHID swap
2-3 = Force FWHID swap
2
C POST-code card. The
2
C signals are from the