Hitachi H8S/2338 Series Hardware Manual page 483

(1) Data write
(2) Transfer from
TDR to TSR
(3) Serial data output
In case of normal transmission: TEND flag is set
In case of transmit error:
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 12-5 Relation Between Transmit Operation and Internal Registers
I/O data
TXI
(TEND interrupt)
When GM = 0
When GM = 1
Legend
Ds : Start bit
D0 to D7 : Data bits
Dp : Parity bit
DE : Error signal
Figure 12-6 TEND Flag Generation Timing in Transmission
TDR
(shift register)
Data 1
Data 1
Data 1
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
TSR
Data 1 ; Data remains in TDR
Data 1
12.5 etu
11.0 etu
I/O signal line output
DE
Guard
time
473