Hitachi H8S/2338 Series Hardware Manual page 111

Figure 4-26 shows the timing when the RCW bit is set to 1.
ø
CSn (RAS)
CAS, LCAS
Figure 4-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a
SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are
output and DRAM enters self-refresh mode, as shown in figure 4-27.
When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is
cleared.
When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is
executed before self-refresh mode is entered.
ø
CSn (RAS)
CAS, LCAS
HWR (WE)
Note: n = 2 to 5
96
T T
Rp Rr
T T
Rp Rcr
Figure 4-27 Self-Refresh Timing
T T
Rc1 Rw
Software
standby
High
T
Rc2
T
Rc3