Hitachi H8S/2338 Series Hardware Manual page 225

Table 6-2 Chain Transfer Conditions
1st Transfer
CHNE CHNS DISEL
0 — 0
0 — 0
0 — 1
1 0 —
1 1 0
1 1 —
1 1 1
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 6-3 outlines the functions of the DTC.
CR CHNE CHNS
Not 0 — —
0 — —
— — —
— 0 —
0 —
0 —
Not 0 — —
0 0 —
0 —
0 —
Not 0 — —
2nd Transfer
DISEL CR
— —
— —
— —
0 Not 0
0 0
1 —
— —
0 Not 0
0 0
1 —
— —
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU
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