Module Stop Control Register (Mstpcr) - Hitachi H8S/2338 Series Hardware Manual

Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*
synchronous clearing through counter clearing on another channel*
Bit n
SYNCn Description
0 TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels)
1 TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
7.2.10

Module Stop Control Register (MSTPCR)

Bit : 15
Initial value : 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and
a transition is made to module stop mode. Registers cannot be read or written to in module stop
mode. For details, see section 19.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 13—Module Stop (MSTP13): Specifies the TPU module stop mode.
Bit 13
MSTP13 Description
0 TPU module stop mode cleared
1 TPU module stop mode set
270
MSTPCRH
14 13 12 11
0 1 1 1
10 9 8 7
1 1 1 1
2
are possible.
MSTPCRL
6 5 4 3
1 1 1 1
1
, and
(Initial value)
n = 5 to 0
2 1 0
1 1 1
(Initial value)