Hitachi H8S/2338 Series Hardware Manual page 663

Table A-2 Instruction Codes (cont)
Instruc-
Mnemonic
tion
SHAR SHAR.B Rd
SHAR.B #2, Rd
SHAR.W Rd
SHAR.W #2, Rd
SHAR.L ERd
SHAR.L #2, ERd
SHLL SHLL.B Rd
SHLL.B #2, Rd
SHLL.W Rd
SHLL.W #2, Rd
SHLL.L ERd
SHLL.L #2, ERd
SHLR SHLR.B Rd
SHLR.B #2, Rd
SHLR.W Rd
SHLR.W #2, Rd
SHLR.L ERd
SHLR.L #2, ERd
SLEEP SLEEP
STC STC.B CCR,Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
Size
1st byte 2nd byte 3rd byte
B 1 1 8 rd
B 1 1 C rd
W 1 1 9 rd
W 1 1 D rd
L 1 1 B 0 erd
L 1 1 F 0 erd
B 1 0 0 rd
B 1
0 4 rd
W 1 0 1 rd
W 1 0 5 rd
L 1 0 erd
0 3
L 1 0 7 0 erd
B 1 1 0 rd
B 1
1 4 rd
W 1 1 1 rd
W 1 1 5 rd
L 1 0 erd
1 3
L 1 1 7 0 erd
— 0 1 8 0
B 0
2 0 rd
B 0 2 1 rd
W 0 1 4 0 6
W 0 1 6
4 1
W 0 1 4 0 6
W 0 1 4 1 6
W 0 1 7
4 0
W 0 1 4 1 7
W 0 1 4 0 6
W 0 1 6
4 1
Instruction Format
4th byte 5th byte 6th byte
9 1 erd 0
9 1 erd 0
F 1 erd 0 disp
F 1 erd 0 disp
8 0 erd 0 6 B A
8 0 erd 0 6 B A
D 1 erd 0
D 1 erd 0
7th byte 8th byte 9th byte
0 disp
0 disp
10th byte