Hitachi H8S/2338 Series Hardware Manual page 326

Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 7-49 shows the timing in this case.
ø
Address
Write signal
Counter clear
signal
TCNT
Figure 7-49 Contention between TCNT Write and Clear Operations
312
TCNT write cycle
T T
1 2
TCNT address
N H'0000