Hitachi H8S/2338 Series Hardware Manual page 190

Full Address Mode (Cycle Steal Mode): Figure 5-20 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
ø
Address bus
RD
HWR
LWR
TEND
Bus release
Figure 5-20 Example of Full Address Mode (Cycle Steal) Transfer
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DMA DMA
read write
Bus release
DMA DMA
read write
Bus release
DMA DMA DMA
read write dead
Last transfer
cycle
Bus
release
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