Hitachi H8S/2338 Series Hardware Manual page 342

Address H'FF4D
Bit :
NDR7
Initial value :
R/W : R/W
Address H'FF4F
Bit :
—
Initial value :
R/W : —
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by
different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and
the address of the lower 4 bits (group 2) is H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4
of address H'FF4E are reserved bits that cannot be modified and are always read as 1.
Address H'FF4C
Bit :
NDR15
Initial value :
R/W : R/W
Address H'FF4E
Bit :
—
Initial value :
R/W : —
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F.
Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be
modified and are always read as 1.
328
7 6
NDR6 NDR5
0 0
R/W R/W
7 6
— —
1 1
— —
7 6
NDR14 NDR13
0 0
R/W R/W
7 6
— —
1 1
— —
5 4
NDR4 NDR3
0 0
R/W R/W
5 4
— —
1 1
— —
5 4
NDR12 —
0 0
R/W —
5 4
— NDR11
1 1
— R/W
3 2
NDR2 NDR1
0 0
R/W R/W
3 2
— —
1 1
— —
3 2
— —
1 1
— —
3 2
NDR10 NDR9
0 0
R/W R/W
1 0
NDR0
0 0
R/W
1 0
—
1 1
—
1 0
—
1 1
—
1 0
NDR8
0 0
R/W