Hitachi H8S/2338 Series Hardware Manual page 331

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T state of a TGR write cycle, the input capture operation takes precedence and the write to
2
TGR is not performed.
Figure 7-54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
Figure 7-54 Contention between TGR Write and Input Capture
TGR write cycle
T T
1 2
TGR address
M
M
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