Table of Contents
Advertisement
4.5.3
Address Multiplexing ...........................................................................................
4.5.4
Data Bus ...............................................................................................................
4.5.5
Pins Used for DRAM Interface ............................................................................ 84
4.5.6
Basic Timing ........................................................................................................ 85
4.5.7
Precharge State Control........................................................................................ 86
4.5.8
Wait Control .........................................................................................................
4.5.9
Byte Access Control .............................................................................................
4.5.10 Burst Operation .................................................................................................... 91
4.5.11 Refresh Control .................................................................................................... 94
4.6
DMAC Single Address Mode and DRAM Interface ........................................................ 97
4.6.1
When DDS = 1 .....................................................................................................
4.6.2
When DDS = 0 .....................................................................................................
4.7
Burst ROM Interface ......................................................................................................... 99
4.7.1
Overview .............................................................................................................. 99
4.7.2
Basic Timing ........................................................................................................ 99
4.7.3
Wait Control ......................................................................................................... 101
4.8
Idle Cycle........................................................................................................................... 102
4.8.1
Operation .............................................................................................................. 102
4.8.2
Pin States in Idle Cycle ........................................................................................ 106
4.9
Write Data Buffer Function ............................................................................................... 107
4.10 Bus Release........................................................................................................................ 108
4.10.1 Overview .............................................................................................................. 108
4.10.2 Operation .............................................................................................................. 108
4.10.3 Pin States in External Bus Released State............................................................ 109
4.10.4 Transition Timing................................................................................................. 110
4.10.5 Usage Note ........................................................................................................... 111
4.11 Bus Arbitration .................................................................................................................. 111
4.11.1 Overview .............................................................................................................. 111
4.11.2 Operation .............................................................................................................. 111
4.11.3 Bus Transfer Timing ............................................................................................ 112
4.11.4 External Bus Release Usage Note ........................................................................ 112
4.12 Resets and the Bus Controller............................................................................................ 112
Section 5
5.1 Overview ................................................................................................................................ 113
5.1.1
Features ................................................................................................................ 113
5.1.2
Block Diagram...................................................................................................... 114
5.1.3
Overview of Functions ......................................................................................... 115
5.1.4
Pin Configuration ................................................................................................. 117
5.1.5
Register Configuration ......................................................................................... 118
5.2
Register Descriptions (1) (Short Address Mode) .............................................................. 119
5.2.1
Memory Address Registers (MAR)...................................................................... 120
5.2.2
I/O Address Register (IOAR)............................................................................... 121
.............................................................................................. 113
83
84
87
89
97
98
iii
Advertisement
Table of Contents
