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ETCRB
Block Transfer Counter
Bit
:
15
Initial value :
*
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the
block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when
the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block
size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any
desired number of bytes or words.
ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
5.3.4
DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
In full address mode, DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
DMACRA
Bit
:
15
DTSZ
Initial value :
R/W
:
R/W
DMACRB
Bit
:
—
Initial value :
R/W
:
R/W
14
13
12
11
*
*
*
*
14
13
SAID
SAIDE
0
0
R/W
R/W
7
6
DAID
DAIDE
0
0
R/W
R/W
10
9
8
7
*
*
*
*
12
11
BLKDIR
BLKE
0
0
R/W
R/W
5
4
—
DTF3
0
0
R/W
R/W
6
5
4
3
*
*
*
*
10
—
—
0
0
R/W
R/W
3
2
DTF2
DTF1
0
0
R/W
R/W
2
1
0
*
*
*
*: Undefined
9
8
—
0
0
R/W
1
0
DTF0
0
0
R/W
133
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