Hitachi H8S/2338 Series Hardware Manual page 470

Bit 7
GM Description
0 Normal smart card interface mode operation
•
TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of
start bit
•
Clock output on/off control only
1 GSM mode smart card interface mode operation
•
TEND flag generation 11.0 etu after beginning of start bit
•
High/low fixing control possible in addition to clock output on/off control (set by
SCR)
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bit 6—Block Transfer Mode (BLK): Selects block transfer mode.
Bit 6
BLK Description
0 Normal smart card interface mode operation
•
Error signal transmission/detection and automatic data retransmission performed
•
TXI interrupt generated by TEND flag
•
TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
1 Block transfer mode operation
•
Error signal transmission/detection and automatic data retransmission not
performed
•
TXI interrupt generated by TDRE flag
•
TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
Bits 3 and 2—Base Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of base
clock periods in a 1-bit transfer interval on the smart card interface.
Bit 3 Bit 2
BCP1 BCP0
0 0
1
1 0
1
Bits 5, 4, 1, and 0—Operate in the same way as for the normal SCI. For details, see section
11.2.5, Serial Mode Register (SMR).
460
Description
32 clock periods
64 clock periods
372 clock periods
256 clock periods
(Initial value)
(Initial value)
(Initial value)