Hitachi H8S/2338 Series Hardware Manual page 365

Bit 7
CMIEB Description
0 CMFB interrupt requests (CMIB) are disabled
1 CMFB interrupt requests (CMIB) are enabled
Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt
requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1.
Bit 6
CMIEA Description
0 CMFA interrupt requests (CMIA) are disabled
1 CMFA interrupt requests (CMIA) are enabled
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests
(OVI) are enabled or disabled when the OVF flag in TCSR is set to 1.
Bit 5
OVIE Description
0 OVF interrupt requests (OVI) are disabled
1 OVF interrupt requests (OVI) are enabled
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by
which TCNT is cleared: by compare match A or B, or by an external reset input.
Bit 4 Bit 3
CCLR1 CCLR0
0 0
1
1 0
1
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (ø): ø/8, ø/64, and ø/8192.
The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
352
Description
Clearing is disabled
Clear by compare match A
Clear by compare match B
Clear by rising edge of external reset input
(Initial value)
(Initial value)
(Initial value)
(Initial value)