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• The division ratio can be changed while the chip is operating. The clock output from the ø pin
will also change when the division ratio is changed. The frequency of the clock output from the
ø pin in this case will be as follows:
ø = EXTAL × n
Where:
EXTAL: Crystal resonator or external clock frequency
n:
• Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
SCK2 to SCK0.
Bit 5
DIV
Description
0
When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
1
When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
Bits 4 and 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of
the clock supplied to the entire chip.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
0
0
0
1
1
0
1
1
0
0
1
1
—
612
Division ratio (n = ø/2, ø/4, or ø/8)
DIV = 0
Bus master is in high-speed
mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
Description
DIV = 1
Bus master is in high-speed
(Initial value)
mode
Clock supplied to entire chip is ø/2
Clock supplied to entire chip is ø/4
Clock supplied to entire chip is ø/8
—
—
—
(Initial value)
(Initial value)
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