Operation; Overview - Hitachi H8S/2338 Series Hardware Manual

8.3

Operation

8.3.1

Overview

PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set
to 1. In this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 8-2 illustrates the PPG output operation and table 8-3 summarizes the PPG operating
conditions.
Pulse output pin
Table 8-3 PPG Operating Conditions
NDER DDR
0 0
1
1 0
1
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before
the next compare match. For details of non-overlapping operation, see section 8.3.4, Non-
Overlapping Pulse Output.
DDR
Q
Normal output/inverted output
Figure 8-2 PPG Output Operation
Pin Function
Generic input port
Generic output port
Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
PPG pulse output
NDER
Q
Output trigger signal
C
Q PODR D Q NDR
Internal data bus
D
335