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3.4.4
Interrupt Exception Handling Sequence .............................................................. 37
3.4.5
Interrupt Response Times.....................................................................................
3.5
Usage Notes .......................................................................................................................
3.5.1
Contention between Interrupt Generation and Disabling.....................................
3.5.2
Instructions that Disable Interrupts ...................................................................... 41
3.5.3
Times when Interrupts are Disabled.....................................................................
3.5.4
Interrupts during Execution of EEPMOV Instruction.......................................... 41
3.6
DTC and DMAC Activation by Interrupt.......................................................................... 42
3.6.1
Overview .............................................................................................................. 42
3.6.2
Block Diagram...................................................................................................... 42
3.6.3
Operation .............................................................................................................. 43
Section 4
4.1
Overview............................................................................................................................ 45
4.1.1
Features ................................................................................................................ 45
4.1.2
Block Diagram...................................................................................................... 47
4.1.3
Pin Configuration .................................................................................................
4.1.4
Register Configuration .........................................................................................
4.2
Register Descriptions.........................................................................................................
4.2.1
Bus Width Control Register (ABWCR) ...............................................................
4.2.2
Access State Control Register (ASTCR).............................................................. 51
4.2.3
Wait Control Registers H and L (WCRH, WCRL).............................................. 52
4.2.4
Bus Control Register H (BCRH).......................................................................... 55
4.2.5
Bus Control Register L (BCRL)...........................................................................
4.2.6
Memory Control Register (MCR) ........................................................................ 60
4.2.7
DRAM Control Register (DRAMCR).................................................................. 62
4.2.8
Refresh Timer Counter (RTCNT) ........................................................................ 64
4.2.9
Refresh Time Constant Register (RTCOR).......................................................... 64
4.3
Overview of Bus Control...................................................................................................
4.3.1
Area Partitioning .................................................................................................. 65
4.3.2
Bus Specifications ................................................................................................ 66
4.3.3
Memory Interfaces................................................................................................ 67
4.3.4
Advanced Mode.................................................................................................... 68
4.3.5
Chip Select Signals...............................................................................................
4.4
Basic Bus Interface............................................................................................................ 70
4.4.1
Overview .............................................................................................................. 70
4.4.2
Data Size and Data Alignment .............................................................................
4.4.3
Valid Strobes ........................................................................................................ 72
4.4.4
Basic Timing ........................................................................................................ 73
4.4.5
Wait Control .........................................................................................................
4.5
DRAM Interface................................................................................................................ 83
4.5.1
Overview .............................................................................................................. 83
4.5.2
Setting DRAM Space ...........................................................................................
ii
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39
40
40
41
48
49
50
50
57
65
69
70
81
83
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