Notes On Register Access - Hitachi H8S/2338 Series Hardware Manual

Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF Description
0 [Clearing condition]
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip if TCNT overflows during watchdog
timer operation.
Bit 6
RSTE Description
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip are
not reset, but TCNT and TCSR within the WDT are reset.
Bit 5— Reserved: Read-only bit.
Bits 4 to 0—Reserved: Read-only bits, always read as 1.
10.2.4

Notes on Register Access

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
They cannot be written to with byte instructions.
Figure 10-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
(Initial value)
(Initial value)
377