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Table A-1 Instruction Set (cont)
(2) Arithmetic Instructions (cont)
Mnemonic
DIVXU
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
DIVXS
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU
EXTU.W Rd
EXTU.L ERd
Addressing Mode/
Instruction Length (Bytes)
B
2
W
2
B
4
W
4
B 2
B
2
W 4
W
2
L 6
L
2
B
2
W
2
L
2
W
2
L
2
Operation
Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — —
RdL: quotient) (unsigned division)
ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — —
Rd: quotient) (unsigned division)
Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — —
RdL: quotient) (signed division)
ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — —
Rd: quotient) (signed division)
Rd8-#xx:8
Rd8-Rs8
Rd16-#xx:16
Rd16-Rs16
ERd32-#xx:32
ERd32-ERs32
0-Rd8→Rd8
0-Rd16→Rd16
0-ERd32→ERd32
0→(<bits 15 to 8> of Rd16)
0→(<bits 31 to 16> of ERd32)
Condition Code
No. of States*
Advanced
I H N Z V C
12
20
13
21
—
1
—
1
— [3]
2
— [3]
1
— [4]
3
— [4]
1
—
1
—
1
—
1
— — 0
0 —
1
— — 0
0 —
1
1
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