Table of Contents
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14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 512
14.2.2 A/D Control/Status Register (ADCSR)................................................................ 513
14.2.3 A/D Control Register (ADCR)............................................................................. 515
14.2.4 Module Stop Control Register (MSTPCR) .......................................................... 516
14.3 Interface to Bus Master...................................................................................................... 517
14.4 Operation ........................................................................................................................... 518
14.4.1 Single Mode (SCAN = 0) ..................................................................................... 518
14.4.2 Scan Mode (SCAN = 1)........................................................................................ 520
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 522
14.4.4 External Trigger Input Timing ............................................................................. 523
14.5 Interrupts............................................................................................................................ 524
14.6 Usage Notes ....................................................................................................................... 525
15.1 Overview............................................................................................................................ 527
15.1.1 Features ................................................................................................................ 527
15.1.2 Block Diagram...................................................................................................... 528
15.1.3 Pin Configuration ................................................................................................. 529
15.1.4 Register Configuration ......................................................................................... 529
15.2 Register Descriptions......................................................................................................... 530
15.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) ................................................. 530
15.2.2 D/A Control Registers 01 and 23 (DACR01, DACR23) ..................................... 530
15.2.3 Module Stop Control Register (MSTPCR) .......................................................... 532
15.3 Operation ........................................................................................................................... 533
16.1 Overview............................................................................................................................ 535
16.1.1 Block Diagram...................................................................................................... 535
16.1.2 Register Configuration ......................................................................................... 536
16.2 Register Descriptions......................................................................................................... 536
16.2.1 System Control Register (SYSCR) ...................................................................... 536
16.3 Operation ........................................................................................................................... 537
16.4 Usage Note ........................................................................................................................ 537
17.1 Overview............................................................................................................................ 539
17.1.1 Block Diagram...................................................................................................... 539
17.1.2 Register Configuration ......................................................................................... 540
17.2 Register Descriptions......................................................................................................... 540
17.2.1 Mode Control Register (MDCR).......................................................................... 540
17.2.2 Bus Control Register L (BCRL)........................................................................... 541
17.3 Operation ........................................................................................................................... 541
17.4 Overview of Flash Memory............................................................................................... 544
x
................................................................................................. 527
................................................................................................................... 535
................................................................................................................... 539
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