Hitachi H8S/2338 Series Hardware Manual page 318

Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 7-36 shows output compare output timing.
ø
TCNT
input clock
TCNT
TGR
Compare
match signal
TIOC pin
Input Capture Signal Timing: Figure 7-37 shows input capture signal timing.
ø
Input capture
input
Input capture
signal
TCNT
TGR
304
N
N
Figure 7-36 Output Compare Output Timing
N
Figure 7-37 Input Capture Input Signal Timing
N+1
N+1 N+2
N N+2