Usage Notes - Hitachi H8S/2338 Series Hardware Manual

Table 19-3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register Bit
MSTPCRH MSTP15
MSTP14
MSTP13
MSTP12
MSTP11
MSTP10
MSTP9
MSTP8
MSTPCRL MSTP7
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
Note: Bits 8 and 3 to 0 can be read or written to, but do not affect operation.
19.5.2

Usage Notes

DMAC*/DTC Module Stop: Depending on the operating status of the DMAC* or DTC, the
MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC* or DTC module stop mode
should be carried out only when the respective module is not activated.
For details, refer to section 5, DMA Controller, and section 6, Data Transfer Controller.
On-Chip Supporting Module Interrupts: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DMAC* or DTC
activation source. Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
Note: * Some models do not have an on-chip DMAC; see the reference manual for the relevant
model for confirmation.
616
Module
DMA controller (DMAC)
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
8-bit timer module
Programmable pulse generator (PPG)
D/A converter (channels 0 and 1)
A/D converter
—
Serial communication interface (SCI) channel 2
Serial communication interface (SCI) channel 1
Serial communication interface (SCI) channel 0
D/A converter (channels 2 and 3)
—
—
—
—