Hitachi H8S/2338 Series Hardware Manual page 697

Table A-6 Instruction Execution Cycles (cont)
1
Instruction
XOR.L ERs,ERd R:W 2nd
XORC #xx:8,CCR R:W NEXT
XORC #xx:8,EXR R:W 2nd
Reset exception Advanced R:W VEC
handling
*
6
Interrupt exception Advanced R:W
handling
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial
value of R4L or R4. If n = 0, these bus cycles are not executed.
3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers.
4. Start address after return.
5. Start address of the program.
6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read
operation is replaced by an internal operation.
7. Start address of the interrupt handling routine.
2 3
R:W NEXT
R:W NEXT
R:W VEC+2 Internal operation, R:W
1 state
Internal operation, W:W stack (L) W:W stack (H)
1 state
4 5 6
*
5
W:W stack (EXR) R:W:M VEC
7 8
R:W VEC+2 Internal operation, R:W
1 state
9
*
7