Hitachi H8S/2338 Series Hardware Manual page 455

Table 11-12 SCI Interrupt Sources
Interrupt
1
Channel* Source
0 ERI
RXI
TXI
TEI
1 ERI
RXI
TXI
TEI
2 ERI
RXI
TXI
TEI
Notes: 1. This table shows the initial state immediate after a reset. Relative priorities among
channels can be changed by the interrupt controller.
2. The number of channels differs from model to model; please check the reference
manual for the relevant model for confirmation.
3. Some models do not support a DMAC; please check the reference manual for the
relevant model for confirmation.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the
result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted
in this case.
444
Description
Interrupt due to receive error
(ORER, FER, or PER)
Interrupt due to receive data full
state (RDRF)
Interrupt due to transmit data empty
state (TDRE)
Interrupt due to transmission end
(TEND)
Interrupt due to receive error
(ORER, FER, or PER)
Interrupt due to receive data full
state (RDRF)
Interrupt due to transmit data empty
state (TDRE)
Interrupt due to transmission end
(TEND)
Interrupt due to receive error
(ORER, FER, or PER)
Interrupt due to receive data full
state (RDRF)
Interrupt due to transmit data empty
state (TDRE)
Interrupt due to transmission end
(TEND)
DTC DMAC*
Activation Activation
Not Not
possible possible
Possible Possible
Possible Possible
Not Not
possible possible
Not Not
possible possible
Possible Possible
Possible Possible
Not Not
possible possible
Not Not
possible possible
Possible Not
possible
Possible Not
possible
Not Not
possible possible
3
2
Priority*
High
Low