Bit
:
—
Initial value :
R/W
:
—
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to
DMACR, DMABCR, and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,
and 3 in DMABCR, and bit 5 in DMATCR, by the DTC.
Bit 3
WE1B
Description
0
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are disabled
1
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are enabled
Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR, by the DTC.
Bit 2
WE1A
Description
0
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled
1
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR, and bit 4 in DMATCR, by the DTC.
Bit 1
WE0B
Description
0
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are disabled
1
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are enabled
7
6
—
—
0
0
—
—
5
4
—
WE1B
0
0
—
R/W
3
2
WE1A
WE0B
0
0
R/W
R/W
1
0
WE0A
0
0
R/W
(Initial value)
(Initial value)
(Initial value)
143