Bus Control Register L (Bcrl); Operation - Hitachi H8S/2338 Series Hardware Manual

17.2.2

Bus Control Register L (BCRL)

Bit :
BRLE
Initial value :
R/W : R/W
Enabling or disabling of part of the on-chip ROM area in the H8S/2338 Series, H8S/2328 Series,
and H8S/2318 Series can be selected by means of the EAE bit in BCRL. For details of the other
bits in BCRL, see section 4.2.5, Bus Control Register L (BCRL).
Bit 5—External Address Enable (EAE): Designates addresses H'010000 to H'03FFFF as either
internal or external addresses.
Bit 5
EAE Description
0 Addresses H'010000 to H'03FFFF*
1 Addresses H'010000 to H'03FFFF*
mode) or a reserved area*
Notes: 1. The on-chip ROM area differs from model to model; please check the reference manual
for the relevant model for confirmation.
2. A reserved area must not be accessed.
17.3

Operation

The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD
EAE bit in BCRL. These settings are shown in table 17-2.
7 6
BREQ0E EAE
0 0
R/W R/W
2
(in single-chip mode)
5 4
— DDS
1 1
R/W R/W
1
are in on-chip ROM
1
are external addresses (in external expanded
3 2
— WDBE
1 1
R/W R/W
, MD , and MD
2 1
1 0
WAITE
0 0
R/W
(Initial value)
) and the
0
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