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Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 7-46 shows
the timing for status flag clearing by the CPU, and figure 7-47 shows the timing for status flag
clearing by the DTC or DMAC.
ø
Address
Write signal
Status flag
Interrupt
request
signal
ø
Address
Status flag
Interrupt
request
signal
Figure 7-47 Timing for Status Flag Clearing by DTC/DMAC Activation
310
Figure 7-46 Timing for Status Flag Clearing by CPU
TSR write cycle
T
T
1
2
TSR address
DTC/DMAC
DTC/DMAC
read cycle
write cycle
T
T
T
1
2
1
Destination
Source address
address
T
2
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