Timer Status Registers (Tsr) - Hitachi H8S/2338 Series Hardware Manual

Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1
TGIEB Description
0 Interrupt requests (TGIB) by TGFB disabled
1 Interrupt requests (TGIB) by TGFB enabled
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA Description
0 Interrupt requests (TGIA) by TGFA disabled
1 Interrupt requests (TGIA) by TGFA enabled
7.2.5

Timer Status Registers (TSR)

Channel 0: TSR0
Channel 3: TSR3
Bit :
—
Initial value :
R/W : —
Note: * Only 0 can be written, to clear the flag.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit :
TCFD
Initial value :
R/W :
Note: * Only 0 can be written, to clear the flag.
264
7 6
— —
1 1
— —
7 6
— TCFU
1 1
R — R/(W)*
5 4
TCFV TGFD
0 0
R/(W)* R/(W)*
5 4
TCFV —
0 0
R/(W)* —
3 2
TGFC TGFB
0 0
R/(W)* R/(W)*
3 2
— TGFB
0 0
— R/(W)*
(Initial value)
(Initial value)
1 0
TGFA
0 0
R/(W)*
1 0
TGFA
0 0
R/(W)*