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10.2
Register Descriptions
10.2.1
Timer Counter (TCNT)
Bit
:
Initial value :
R/W
:
R/W
TCNT is an 8-bit readable/writable*
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)*
interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Notes: 1. TCNT is write-protected by a password to prevent accidental overwriting. For details
see section 10.2.4, Notes on Register Access.
2. The WDTOVF output function is not available in all models; please check the
reference manual for the relevant model for confirmation.
10.2.2
Timer Control/Status Register (TCSR)
Bit
:
OVF
Initial value :
R/W
:
R/(W)*
Note: * Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 10.2.4, Notes on Register Access.
374
7
6
0
0
R/W
R/W
1
up-counter.
7
6
WT/IT
TME
0
0
R/W
R/W
5
4
0
0
R/W
R/W
5
4
—
—
0
1
—
—
3
2
0
0
R/W
R/W
2
or an interval timer
3
2
CKS2
CKS1
1
0
R/W
R/W
1
0
0
0
R/W
1
0
CKS0
0
0
R/W
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