Hitachi H8S/2338 Series Hardware Manual page 581

Error protection is released only by a reset and in hardware standby mode.
Figure 17-16 shows the flash memory state transition diagram.
Normal operating mode
Program mode
Erase mode
RD VF PR ER
FLER = 0
Error
occurrence
Error protection mode
RD VF PR ER
FLER = 1
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RES = 0 or STBY = 0
Error occurrence
(software standby)
Software
standby mode
Software standby
mode release
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 17-16 Flash Memory State Transitions
Reset or hardware standby
(hardware protection)
RD VF PR ER
RES = 0 or
STBY = 0
RES = 0 or
STBY = 0
Error protection mode
(software standby)
RD VF PR ER
FLER = 1
FLMCR1, FLMCR2 (except FLER
bit), EBR1, EBR2 initialization state
FLER = 0
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
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