Hitachi H8S/2338 Series Hardware Manual page 195

DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 5-25 shows an example of DREQ level activated normal mode transfer.
ø
DREQ
Address
bus
DMA
Idle
control
Channel Request
of 2 cycles
[1]
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø,
[1]
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 5-25 Example of DREQ Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
180
Bus DMA
read
release
Transfer source
Read Write
Request clear period
Minimum
[2] [3]
DMA Bus
write
release
Transfer destination
Idle
Request
Minimum
of 2 cycles
[4] [5]
Acceptance resumes
DMA DMA
read write
Transfer source Transfer destination
Read Write Idle
Request clear period
[6]
Acceptance resumes
Bus
release
[7]