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Signal Integrity Recommendations and
Simulations
This chapter provides summaries of the termination schemes for various signals and
discusses IBIS simulations. It contains the following sections:
•
•
Termination and Transmission Line Summaries
The following bulleted items provide recommendations for the signal termination scheme
to the seven different external memories implemented on the Virtex-4 ML461
Development Board:
•
•
•
•
Virtex-4 ML461 Development Board
UG079 (v1.1) September 5, 2007
"Termination and Transmission Line Summaries"
"IBIS Simulations"
Single-ended signals: Simulation indicates that for a single-ended signal, there is no
significant performance difference for a signal with split termination of 100Ω + 100Ω
between VDD and GND versus the V
Because the power consumption for the split termination is considerably higher than
the V
termination for the SSTL2, SSTL18, and HSTL I/O standards, V
TT
is recommended for single-ended signals on the board, such as data, address, and
control.
Differential signals: For differential pair signals, a 100Ω differential termination is
provided between the two legs of the differential pair. This termination is placed
closest to the load.
Bidirectional signals: For bidirectional single-ended signals, for example, DDR2 DQ,
the V
termination is provided at both ends of the signal, that is, at the FPGA as well
TT
as at the memory. For differential bidirectional signals, for example, DDR2 DQS, the
newly introduced differential SelectIO™ primitives in Virtex-4 FPGAs, for example,
DIFF_SSTL_II_18_DCI, account for the differential termination within the IOB. So
external differential termination at the FPGA is not required.
Multiload signals: Address and control signals are driven by the FPGA, and they
have multiple loads. The termination is placed at the end of the trace after the last
load.
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termination of 50Ω to the V
TT
Chapter 5
voltage.
REF
termination
TT
49
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