Xilinx Virtex-4 ML461 User Manual page 35

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Table 3-15: ML461 Revision B PCB Controlled Impedance
Layer Name
1
2 TOP
3
4 GND1
5
6 PWR1
7
8 InnerSignal1
9
10 GND1a
11
12 InnerSignal2
13
14 GND2
15
16 PWR2
17
18 InnerSignal3
19
20 InnerSignal4
21
22 GND4
23
24 PWR3
25
26 InnerSignal5
27
28 GND5a
29
30 InnerSignal6
31
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Type Usage
Dielectric Solder Mask
Metal Signal
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Signal
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Signal
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Signal
Dielectric Substrate
Metal Signal
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Signal
Dielectric Substrate
Metal Solid Plane
Dielectric Substrate
Metal Signal
Dielectric Substrate
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Board Design Considerations
Thickness
Er
(mils)
1.3 3.3
1.338 <Auto>
4 4.3
1.338 <Auto>
4 4.3
1.338 <Auto>
5 3.9
0.669 <Auto>
5 3.9
1.338 <Auto>
5 3.9
0.669 <Auto>
5 3.9
1.338 <Auto>
4 4.3
1.338 <Auto>
4 3.9
0.669 <Auto>
4 3.9
0.669 <Auto>
4 3.9
1.338 <Auto>
4 4.3
1.338 <Auto>
5 3.9
0.669 <Auto>
5 3.9
1.338 <Auto>
5 3.9
0.669 <Auto>
5 3.9
Test
Width Z0Ω
(mils)
5 54.3
4 51.3
4 51.3
4 53.2
4 53.2
4 51.3
4 51.3
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