Xilinx Virtex-4 ML461 User Manual page 79

Memory interfaces
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Table A-4: FPGA #4 Pinout (Continued)
Signal Name
LVDS_RX17
LVDS_RX18
LVDS_RX19
SFP1_TXN
SFP2_TXP
SFP2_TXN
XEN_TX0P
XEN_TX0N
XEN_TX1P
XEN_TX1N
XEN_TX2P
XEN_TX2N
XEN_TX3P
XEN_TX3N
LVDS_RX0
LVDS_RX1
LVDS_RX2
LVDS_RX3
LVDS_RX4
LVDS_RX5
LVDS_RX6
LVDS_RX7
LVDS_RX8
LVDS_RX9
LVDS_RX10
LVDS_RX11
LVDS_RX12
LVDS_RX13
LVDS_RX14
LVDS_RX15
LVDS_RX16
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
Z-DOK+ Connector Interface (cont'd)
AB4
LVDS_RX17
AC5
LVDS_RX18
AB5
LVDS_RX19
T3
LVDS_RX20
T7
LVDS_RX21
T6
LVDS_RX22
V4
LVDS_RX23
U4
LVDS_RX24
V2
LVDS_RX25
V1
LVDS_RX26
T8
LVDS_RX27
U7
LVDS_RX28
U6
LVDS_RX29
U5
LVDS_RX30
W2
LVDS_RX31
W1
RXP0CLKP_C2
V6
RXP0CLKN_C2
V5
LVDS_CLKEXT_P
W7
LVDS_CLKEXT_N
V7
LVDS_CLKEXT_P
W6
LVDS_CLKEXT_N
W5
SFP0_RXP
Y2
SFP0_RXN
Y1
SFP1_RXP
AA4
SFP1_RXN
AA3
SFP2_RXP
Y6
SFP2_RXN
Y5
SMA_RXP
AB1
SMA_RXN
AA1
XEN_RX0P
AC4
XEN_RX0N
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FPGA #4 Pinout
Signal Name
Pin
AB4
AC5
AB5
AC2
AC1
AF3
AE3
AF4
AE4
AD3
AC3
AF6
AF5
AA9
Y9
Y4
Y3
AD2
AD1
AC6
AB6
AF8
AF7
AA8
Y8
Y10
AA10
AC7
AB7
AC9
AB9
79

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