Xilinx Virtex-4 ML461 User Manual page 75

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Table A-3: FPGA #3 Pinout (Continued)
Signal Name
FPGA3_TEST_HDR_BY0_B0
FPGA3_TEST_HDR_BY0_B1
FPGA3_TEST_HDR_BY0_B2
FPGA3_TEST_HDR_BY0_B3
FPGA1_SYNTH_S_CLK
FPGA1_SYNTH_S_DATA
FPGA1_SYNTH_S_LOAD
FPGA2_SYNTH_S_CLK
FPGA2_SYNTH_S_DATA
CLOCK_SYNTH_MASTER_RESET
FPGA2_SYNTH_S_LOAD
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Pin
FPGA #3 Test Header Signals
A12 FPGA3_TEST_HDR_BY0_B4
A11 FPGA3_TEST_HDR_BY0_B5
B13 FPGA3_TEST_HDR_BY0_B6
B12 FPGA3_TEST_HDR_BY0_B7
Clock Synthesizer Control Signals
F14 FPGA3_SYNTH_S_CLK
F13 FPGA3_SYNTH_S_DATA
F12 FPGA3_SYNTH_S_LOAD
F16 FPGA4_SYNTH_S_CLK
F15 FPGA4_SYNTH_S_DATA
D12 FPGA4_SYNTH_S_LOAD
D14
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FPGA #3 Pinout
Signal Name Pin
A10
B10
B17
A17
D15
E14
C11
D16
C16
E13
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