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Table 4-8: Estimated Power Consumption
Configuration Image
DDR1 Registered DIMM 144-
bit Design
DDR2 Registered DIMM 144-
bit Design using
SSTL18_II_DCI for DQ and
ODT on DDR2 Memory
RLDRAM_II 72-bit Design
(not implemented on the
ML461)
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
Freq
1.2V
2.5V
3.3V
(MHz)
200
1.68
4.25
2.64
267
2.04
4.50
1.98
267
1.6
2.75
1.98
www.xilinx.com
Power Measurements on the ML461
Power Consumption (Watts)
SSTL18
SSTL2
HSTL
1.8V
2.6V
1.8V
1.62
13.26
0.18
14.94
2.86
0.18
1.98
2.86
2.34
TOTAL
Design
23.63
19.98
26.50
19.85
13.59
6.94
47
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